Grants and Contracts Details
Although Si and GaAs have been used to create po\verful VLSI circuits, their fabrication is a relatively expensive process. Only circuits that have large volume productions (and markets) are profitable to fabricate. Through the use of a nano-scaled template, the cost of fabrication can be reduced and the density of logical gates increased. We propose to demonstrate the feasibility of nano-sized digital circuitry by fabricating Metal Oxide Semiconductor (MOS) transistors. This will be done on a porous alumina template. Initially, the transistors will have a common node (SOURCE or DRAIN), on top of which the template will be fabricated. Through etching (chemical or e-beam), trenches on the template will be created and re-filled with a metal, these will serve as the gate.
|Effective start/end date
|5/1/05 → 12/31/07
- KY Science and Technology Co Inc: $99,951.00
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