KSEF RDE: Energy Efficient Digital Signal Processor Based On Reversible Nanomagnetic Logic

Dedicated digital signal processors (DSP) can speed-up the processing of complex DSP applications. Unfortunately, high speed processing has high electricity budget which can exceed millions of dollars. According to a recent fundamental contribution, to reduce the energy dissipated in switching a logic device, there are two distinct paths: (i) the first path is to reduce the energy that is stored in the device to distinguish a digital 1 from a 0, (ii) the other path is to conserve that energy from one logical operation to the next. Spintronics based Nanomagnetic logic (NML) satisfies the first path while reversible logic based on energy recovery concept satisfies the second path. Hence, the PI will develop Spintronics (Nanomagnetic Logic-NML) and reversible logic based digital signal processor that will be energy efficient in nature. The objectives of the proposed research are as follows: (i) Investigate Spintronics devices to implement energy efficient computing units such as adder, multiplier, arithmetic logic unit (ALU), etc. (ii) Investigate Spintronics devices to design energy efficient memory elements such as latches, flip-flops, and random access memory (RAM). (iii) Investigate reversible computing paradigm to further optimize the energy efficiency of Spintronics-based NML computing and memory units. (iv) Integrate the computing and memory units designed in Steps (i)-(iii) to implement DSP functions such as Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT). (v) Integrate the Steps (i)-(iv) to design energy efficient digital signal processors The proposed research will advance computing education and research in the following ways: (i) development of intellectual products and libraries for the energy efficient nanocomputing, (ii) educate and mentor computer science, computer engineering and electrical engineering students about the post-cmos technologies and prepare them to do research in these areas