Supplement: EAGER: Transforming Optical Neural Network Accelerators with Stochastic Computing

Re: Request for Supplements for Access to Semiconductor Fabrication (ASF) Award ID 2139167 Title: EAGER: Transforming Optical Neural Network Accelerators with Stochastic Computing PI: Ishan Thakkar One of the objectives of this currently active project is to validate our designed microring resonator-based gate called MRR-PEOLG. To achieve this objective, our planned activity involves prototyping our MRR- PEOLG using the electron-beam lithography-based fabrication process available to us at KY Multiscale. However, we propose to extend this device validation objective through this request for supplemental funding. For that, we propose to undertake the prototyping and fabrication of our MRR-PEOLG at a commercial silicon-photonic foundry AMF via CMC Microsystems, using their standard silicon photonics fabrication process. Our rationale behind this proposal is two-fold. First, we reason that although our planned use of the electron-beam lithography-based fabrication process at KY Multiscale will provide rapid prototyping and validation of our MRR-PEOLG, a more credible and useful validation is required to prove the mass producibility and commercial feasibility of our MRR-PEOLG. We expect to obtain such validation through our proposed fabrication activity at CMC Microsystems. Second, compared to our originally planned fabrication at KY Multiscale, our proposed fabrication at CMC Microsystems will enable a more realistic characterization of the device-layer performance bounds of our MRR-PEOLG in terms of its achievable operating speed (data rate) and power consumption. We expect these device-layer performance bounds to consequently enable accurate performance estimates for our envisioned reconfigurable optical circuits and systems. With these rationales, we will aim to utilize the requested supplemental funding to fabricate our designed MRR-PEOLGs, with up to 10 MRR-PEOLGs per chip, using the MPW runs offered by CMC Microsystems. After the fabricated MRR-PEOLG chips are available to us from CMC Microsystems, we will undertake the following two outstanding research tasks during the current reporting period of the active NSF grant: (i) Characterize the device-layer performance bounds of the fabricated MRR-PEOLGs by employing the characterization and testing tools available to us at KY Multiscale; and (ii) Develop a portable, Verilog-A based, and compact behavioral model of our MRR-PEOLG by correlating the characterized device-layer performance bounds of the fabricated MRR-PEOLGs with their measured physical design parameters such as MRR radius, cross-sectional dimensions, and coupling gap. Note that the above two tasks are not newly proposed tasks; these tasks were to be undertaken using the MRR-PEOLG chips fabricated at KY Multiscale. But we will now undertake these tasks using the MRR-PEOLG chips that we will fabricate through CMC Microsystems utilizing the requested supplementary funds.