3-D wired: A novel wide i/o dram with energy-efficient 3-D Bank Organization

Ishan Thakkar, Sudeep Pasricha

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

A novel WIDE I/O DRAM architecture called 3-D WiRED is proposed, with an enhanced DRAM core to enable low latency and energy-efficient memory access. Through detailed time-energy analysis of a WIDE I/O DRAM prototype, we have identified the need to reduce the capacitance of bitlines (BLs), memory bus (M_bus), and global data path to reduce random access latency, read/write energy, and activation-precharge (ActPre) energy. Trace-driven simulation analysis was performed to compare 3-DWiRED with other state-of-the-art DRAM architectures. Memory access traces for the PARSEC benchmark suite were extracted from detailed cycle-accurate simulations using gem5. rank-based round-robin scheduling scheme and a closed page policy were used for all simulations. Energy-per-bit, average-latency, and energy-delay product values for the memory subsystem were obtained from DRAMSim2. The results indicate that the performance and energy efficiency of contemporary wide I/O DRAM core can be greatly improved by aggressively using TSVs at subarray-level granularity. However, several challenges still need to be overcome to support such a fine-grained 3-D integration.

Original languageEnglish
Article number7116520
Pages (from-to)71-80
Number of pages10
JournalIEEE Design and Test
Volume32
Issue number4
DOIs
StatePublished - 2015

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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