This paper introduces 3D-ProWiz, which is a high-bandwidth, energy-efficient, optically-interfaced 3D DRAM architecture with fine grained data organization and activation. 3D-ProWiz integrates sub-bank level 3D partitioning of the data array to enable fine-grained activation and greater memory parallelism. A novel method of routing the internal memory bus to individual subarrays using TSVs and fanout buffers enables 3D-ProWiz to use smaller dimension subarrays without significant area overhead. The use of TSVs at subarray-level granularity eliminates the need to use slow and power hungry global lines, which in turn reduces the random access latency and activation-precharge energy. 3D-ProWiz yields the best latency and energy consumption values per access among other well-known 3D DRAM architectures. Experimental results with PARSEC benchmarks indicate that 3D-ProWiz achieves 41.9 percent reduction in average latency, 52 percent reduction in average power, and 80.6 percent reduction in energy-delay product (EDP) on average over DRAM architectures from prior work.
|Number of pages||17|
|Journal||IEEE Transactions on Multi-Scale Computing Systems|
|State||Published - 2015|
Bibliographical noteFunding Information:
This research is supported by grants from SRC, the US National Science Foundation (NSF) (CCF-1252500, CCF-1302693), and AFOSR (FA9550-13-1-0110).
© 2015 IEEE.
- Fine-grained activation
- fanout buffers
ASJC Scopus subject areas
- Control and Systems Engineering
- Information Systems
- Hardware and Architecture