Abstract
This paper introduces 3D-Wiz, which is a high bandwidth, low latency, optically interfaced 3D DRAM architecture with fine grained data organization and activation. 3D-Wiz integrates sub-bank level 3D partitioning of the data array to enable fine-grained activation and greater memory parallelism. A novel method of routing the internal memory bus using TSVs and fan-out buffers enables 3D-Wiz to use smaller dimension subarrays without significant area overhead. This in turn reduces the random access latency and activation-precharge energy. 3D-Wiz demonstrates access latency of 19.5ns and row cycle time of 25ns. It yields per access activation energy and precharge energy of 0.78nJ and 0.62nJ respectively with 42.5% area efficiency. 3D-Wiz yields the best latency and energy consumption values per access among other well-known 3D DRAM architectures. Experimental results with PARSEC benchmarks indicate that 3D-Wiz achieves 38.8% improvement in performance, 81.1% reduction in power consumption, and 77.1% reduction in energy-delay product (EDP) on average over 3D DRAM architectures from prior work.
Original language | English |
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Title of host publication | 2014 32nd IEEE International Conference on Computer Design, ICCD 2014 |
Pages | 1-7 |
Number of pages | 7 |
ISBN (Electronic) | 9781479964925 |
DOIs | |
State | Published - Dec 3 2014 |
Event | 32nd IEEE International Conference on Computer Design, ICCD 2014 - Seoul, Korea, Republic of Duration: Oct 19 2014 → Oct 22 2014 |
Publication series
Name | 2014 32nd IEEE International Conference on Computer Design, ICCD 2014 |
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Conference
Conference | 32nd IEEE International Conference on Computer Design, ICCD 2014 |
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Country/Territory | Korea, Republic of |
City | Seoul |
Period | 10/19/14 → 10/22/14 |
Bibliographical note
Publisher Copyright:© 2014 IEEE.
ASJC Scopus subject areas
- Computer Graphics and Computer-Aided Design
- Computer Science Applications