A Bit-Parallel Deterministic Stochastic Multiplier

Sairam Sri Vatsavai, Ishan Thakkar

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents a novel bit-parallel deterministic stochastic multiplier, which improves the area-energy-latency product by up to 10.6×104, while improving the computational error by 32.2%, compared to three prior stochastic multipliers.

Original languageEnglish
Title of host publicationProceedings of the 24th International Symposium on Quality Electronic Design, ISQED 2023
ISBN (Electronic)9798350334753
DOIs
StatePublished - 2023
Event24th International Symposium on Quality Electronic Design, ISQED 2023 - San Francisco, United States
Duration: Apr 5 2023Apr 7 2023

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2023-April
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference24th International Symposium on Quality Electronic Design, ISQED 2023
Country/TerritoryUnited States
CitySan Francisco
Period4/5/234/7/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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