A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects

Ishan G. Thakkar; Sai Vineel Reddy Chittamuru; Sudeep Pasricha

doi:10.1145/2947357.2947362

A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects

Ishan G. Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

19 Scopus citations

Abstract

Photonic devices fabricated with back-end compatible silicon photonic (BCSP) materials can provide independence from the complex CMOS front-end compatible silicon photonic (FCSP) process, to significantly enhance photonic network-on-chip (PNoC) architecture performance. In this paper, we present a detailed comparative analysis of a number of design tradeoffs for CMOS front-end and backend compatible devices for silicon photonic interconnects. A crosslayer optimization of multiple device-level and link-level design parameters is performed to enable the design of energy-efficient on-chip photonic interconnects using BCSP devices. The optimized design of BCSP on-chip links renders more energy-efficiency and aggregate bandwidth than FCSP on-chip links, in spite of the inferior opto-electronic properties of BCSP devices. Our experimental analysis compares the use of BCSP and FCSP links at the architecture level, and shows that the optimized design of the BCSP-based Firefly PNoC achieves 1.15× greater throughput and 12.4% less energy-per-bit on average than the optimized design of FCSP-based Firefly PNoC. Similarly, the optimized design of the BCSP-based Corona PNoC achieves 3.5× greater throughput and 39.5% less energy-per-bit on average than the optimized design of FCSP-based Corona PNoC.

Original language	English
Title of host publication	Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016
ISBN (Electronic)	9781450344302
DOIs	https://doi.org/10.1145/2947357.2947362
State	Published - Jun 4 2016
Event	2016 18th ACM/IEEE System Level Interconnect Prediction Workshop, SLIP 2016 - Austin, United States Duration: Jun 4 2016 → …

Publication series

Name	Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016

Conference

Conference	2016 18th ACM/IEEE System Level Interconnect Prediction Workshop, SLIP 2016
Country/Territory	United States
City	Austin
Period	6/4/16 → …

Bibliographical note

Publisher Copyright:
© 2016 ACM.

Keywords

Aggregate bandwidth
Design tradeoffs
Energy efficiency
Optimization
Photonic network on chip

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Hardware and Architecture
Applied Mathematics

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1145/2947357.2947362

Cite this

Thakkar, I. G., Chittamuru, S. V. R., & Pasricha, S. (2016). A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects. In Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016 Article 2947362 (Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016). https://doi.org/10.1145/2947357.2947362

Thakkar, Ishan G. ; Chittamuru, Sai Vineel Reddy ; Pasricha, Sudeep. / A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects. Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016. 2016. (Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016).

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abstract = "Photonic devices fabricated with back-end compatible silicon photonic (BCSP) materials can provide independence from the complex CMOS front-end compatible silicon photonic (FCSP) process, to significantly enhance photonic network-on-chip (PNoC) architecture performance. In this paper, we present a detailed comparative analysis of a number of design tradeoffs for CMOS front-end and backend compatible devices for silicon photonic interconnects. A crosslayer optimization of multiple device-level and link-level design parameters is performed to enable the design of energy-efficient on-chip photonic interconnects using BCSP devices. The optimized design of BCSP on-chip links renders more energy-efficiency and aggregate bandwidth than FCSP on-chip links, in spite of the inferior opto-electronic properties of BCSP devices. Our experimental analysis compares the use of BCSP and FCSP links at the architecture level, and shows that the optimized design of the BCSP-based Firefly PNoC achieves 1.15× greater throughput and 12.4% less energy-per-bit on average than the optimized design of FCSP-based Firefly PNoC. Similarly, the optimized design of the BCSP-based Corona PNoC achieves 3.5× greater throughput and 39.5% less energy-per-bit on average than the optimized design of FCSP-based Corona PNoC.",

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Thakkar, IG, Chittamuru, SVR & Pasricha, S 2016, A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects. in Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016., 2947362, Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016, 2016 18th ACM/IEEE System Level Interconnect Prediction Workshop, SLIP 2016, Austin, United States, 6/4/16. https://doi.org/10.1145/2947357.2947362

A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects. / Thakkar, Ishan G.; Chittamuru, Sai Vineel Reddy; Pasricha, Sudeep.
Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016. 2016. 2947362 (Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Thakkar IG, Chittamuru SVR, Pasricha S. A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects. In Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016. 2016. 2947362. (Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016). doi: 10.1145/2947357.2947362

A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

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