A fine-grain parallel architecture based on barrier synchronization

H. G. Dietz; R. Hoare; T. Mattox

doi:10.1109/ICPP.1996.539061

A fine-grain parallel architecture based on barrier synchronization

H. G. Dietz, R. Hoare, T. Mattox

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Citations (SciVal)

Abstract

Although barrier synchronization has long been considered a useful construct for parallel programming, it has generally been either layered on top of a communication system or used as a completely independent mechanism. Instead, we propose that all communication be made a side-effect of barrier synchronization. This is done by extending the barrier synchronization unit to collect a datum from each processor, compute an aggregate function, and return the corresponding result to each processor. This paper describes a scalable prototype implementation of PAPERS (Purdue's Adapter for Parallel Execution and Rapid Synchronization). Despite the fact that the prototype is implemented as very simple TTL hardware connecting conventional workstations, measured performance on fine-grain parallel communication operations is far superior to that obtained using conventional workstation networks. It is comparable to the performance of commercially available supercomputers.

Original language	English
Title of host publication	Architecture
Editors	A. Reeves
Pages	247-250
Number of pages	4
ISBN (Electronic)	081867623X
DOIs	https://doi.org/10.1109/ICPP.1996.539061
State	Published - 1996
Event	25th International Conference on Parallel Processing, ICPP 1996 - Ithaca, United States Duration: Aug 12 1996 → Aug 16 1996

Publication series

Name	Proceedings of the International Conference on Parallel Processing
Volume	1
ISSN (Print)	0190-3918

Conference

Conference	25th International Conference on Parallel Processing, ICPP 1996
Country/Territory	United States
City	Ithaca
Period	8/12/96 → 8/16/96

Bibliographical note

Funding Information:
This work was supported in part by ONR Grant No. N0001-91-J-4013 and NSF Grant No. CDA-9015696.

Publisher Copyright:
© 1996 IEEE.

ASJC Scopus subject areas

Software
Mathematics (all)
Hardware and Architecture

Access to Document

10.1109/ICPP.1996.539061

Cite this

@inproceedings{633023df065a464f96649876d7ef2158,

title = "A fine-grain parallel architecture based on barrier synchronization",

abstract = "Although barrier synchronization has long been considered a useful construct for parallel programming, it has generally been either layered on top of a communication system or used as a completely independent mechanism. Instead, we propose that all communication be made a side-effect of barrier synchronization. This is done by extending the barrier synchronization unit to collect a datum from each processor, compute an aggregate function, and return the corresponding result to each processor. This paper describes a scalable prototype implementation of PAPERS (Purdue's Adapter for Parallel Execution and Rapid Synchronization). Despite the fact that the prototype is implemented as very simple TTL hardware connecting conventional workstations, measured performance on fine-grain parallel communication operations is far superior to that obtained using conventional workstation networks. It is comparable to the performance of commercially available supercomputers.",

author = "Dietz, {H. G.} and R. Hoare and T. Mattox",

note = "Funding Information: This work was supported in part by ONR Grant No. N0001-91-J-4013 and NSF Grant No. CDA-9015696. Publisher Copyright: {\textcopyright} 1996 IEEE.; 25th International Conference on Parallel Processing, ICPP 1996 ; Conference date: 12-08-1996 Through 16-08-1996",

year = "1996",

doi = "10.1109/ICPP.1996.539061",

language = "English",

series = "Proceedings of the International Conference on Parallel Processing",

pages = "247--250",

editor = "A. Reeves",

booktitle = "Architecture",

}

Dietz, HG, Hoare, R & Mattox, T 1996, A fine-grain parallel architecture based on barrier synchronization. in A Reeves (ed.), Architecture., 539061, Proceedings of the International Conference on Parallel Processing, vol. 1, pp. 247-250, 25th International Conference on Parallel Processing, ICPP 1996, Ithaca, United States, 8/12/96. https://doi.org/10.1109/ICPP.1996.539061

TY - GEN

T1 - A fine-grain parallel architecture based on barrier synchronization

AU - Dietz, H. G.

AU - Hoare, R.

AU - Mattox, T.

PY - 1996

Y1 - 1996

N2 - Although barrier synchronization has long been considered a useful construct for parallel programming, it has generally been either layered on top of a communication system or used as a completely independent mechanism. Instead, we propose that all communication be made a side-effect of barrier synchronization. This is done by extending the barrier synchronization unit to collect a datum from each processor, compute an aggregate function, and return the corresponding result to each processor. This paper describes a scalable prototype implementation of PAPERS (Purdue's Adapter for Parallel Execution and Rapid Synchronization). Despite the fact that the prototype is implemented as very simple TTL hardware connecting conventional workstations, measured performance on fine-grain parallel communication operations is far superior to that obtained using conventional workstation networks. It is comparable to the performance of commercially available supercomputers.

AB - Although barrier synchronization has long been considered a useful construct for parallel programming, it has generally been either layered on top of a communication system or used as a completely independent mechanism. Instead, we propose that all communication be made a side-effect of barrier synchronization. This is done by extending the barrier synchronization unit to collect a datum from each processor, compute an aggregate function, and return the corresponding result to each processor. This paper describes a scalable prototype implementation of PAPERS (Purdue's Adapter for Parallel Execution and Rapid Synchronization). Despite the fact that the prototype is implemented as very simple TTL hardware connecting conventional workstations, measured performance on fine-grain parallel communication operations is far superior to that obtained using conventional workstation networks. It is comparable to the performance of commercially available supercomputers.

UR - http://www.scopus.com/inward/record.url?scp=0038620887&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0038620887&partnerID=8YFLogxK

U2 - 10.1109/ICPP.1996.539061

DO - 10.1109/ICPP.1996.539061

M3 - Conference contribution

AN - SCOPUS:0038620887

T3 - Proceedings of the International Conference on Parallel Processing

SP - 247

EP - 250

BT - Architecture

A2 - Reeves, A.

T2 - 25th International Conference on Parallel Processing, ICPP 1996

Y2 - 12 August 1996 through 16 August 1996

ER -

A fine-grain parallel architecture based on barrier synchronization

Abstract

Publication series

Conference

Bibliographical note

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this