A fine-grain parallel architecture based on barrier synchronization

H. G. Dietz, R. Hoare, T. Mattox

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Citations (SciVal)


Although barrier synchronization has long been considered a useful construct for parallel programming, it has generally been either layered on top of a communication system or used as a completely independent mechanism. Instead, we propose that all communication be made a side-effect of barrier synchronization. This is done by extending the barrier synchronization unit to collect a datum from each processor, compute an aggregate function, and return the corresponding result to each processor. This paper describes a scalable prototype implementation of PAPERS (Purdue's Adapter for Parallel Execution and Rapid Synchronization). Despite the fact that the prototype is implemented as very simple TTL hardware connecting conventional workstations, measured performance on fine-grain parallel communication operations is far superior to that obtained using conventional workstation networks. It is comparable to the performance of commercially available supercomputers.

Original languageEnglish
Title of host publicationArchitecture
EditorsA. Reeves
Number of pages4
ISBN (Electronic)081867623X
StatePublished - 1996
Event25th International Conference on Parallel Processing, ICPP 1996 - Ithaca, United States
Duration: Aug 12 1996Aug 16 1996

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918


Conference25th International Conference on Parallel Processing, ICPP 1996
Country/TerritoryUnited States

Bibliographical note

Funding Information:
This work was supported in part by ONR Grant No. N0001-91-J-4013 and NSF Grant No. CDA-9015696.

Publisher Copyright:
© 1996 IEEE.

ASJC Scopus subject areas

  • Software
  • Mathematics (all)
  • Hardware and Architecture


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