A High Speed Efficient N X N Bit Multiplier based on Ancient Indian Vedic Mathematics

Vishal Verma, Himanshu Thapliyal

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

A N X N high speed, efficient fully synthesizable multiplier based on algorithm of ancient Indian Mathematics called Vedic Mathematics is presented in this paper. The design implementation is described in both at gate level and high level RTL code (behavioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopsis FPGA Express using: Xilinx, Family: Spartan Svq300, Speed Grade: -6. The design is completely technology independent and can be easily converted from one technology to another. The present paper relates to the field of math coprocessors in computers and more specifically to improvement in speed and power over multiplication algorithm implemented in coprocessors. In FPGA implementation it has been found that Vedic multiplier is faster than array multiplier.

Original languageEnglish
Title of host publicationProceedings of the International Conference on VLSI, VLSI 03
EditorsH.R. Arbania, L.T. Yang
Pages361-365
Number of pages5
StatePublished - 2003
EventProceedings of the International Conference on VLSI, VLSI'03 - Las Vegas, NV, United States
Duration: Jun 23 2003Jun 26 2003

Publication series

NameProceedings of the International Conference on VLSI

Conference

ConferenceProceedings of the International Conference on VLSI, VLSI'03
Country/TerritoryUnited States
CityLas Vegas, NV
Period6/23/036/26/03

Keywords

  • Array Multiplier
  • Multiplier
  • Vedic Mathematics

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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