A need of quantum computing: "Reversible logic synthesis of parallel binary adder-subtractor"

Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

Earlier research has proved that a finite amount of energy dissipation would occur if the computation is devoid of reversible logic. In the light of this problem, a binary parallel adder-subtractor using reversible logic is proposed. The proposed circuit has the ability to add and subtract two 4-bit binary numbers depending on the mode bit M. This circuit can be generalized for N bit addition and subtraction. The proposed design technique uses minimum number of gates as well as garbage outputs thereby significantly reducing the circuit complexity.

Original languageEnglish
Title of host publicationProceedings of the 2005 International Conference on Embedded Systems and Applications, ESA'05
Pages60-66
Number of pages7
StatePublished - 2005
Event2005 International Conference on Embedded Systems and Applications, ESA'05 - Las Vegas, NV, United States
Duration: Jun 27 2005Jun 30 2005

Publication series

NameProceedings of the 2005 International Conference on Embedded Systems and Applications, ESA'05

Conference

Conference2005 International Conference on Embedded Systems and Applications, ESA'05
Country/TerritoryUnited States
CityLas Vegas, NV
Period6/27/056/30/05

Keywords

  • Reversible logic
  • Reversible parallel binary adder- Subtractor
  • Reversible subtractor

ASJC Scopus subject areas

  • Artificial Intelligence
  • Hardware and Architecture
  • Control and Systems Engineering

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