TY - GEN
T1 - A new design of the reversible subtractor circuit
AU - Thapliyal, Himanshu
AU - Ranganathan, Nagarajan
PY - 2011
Y1 - 2011
N2 - In [1] we have presented the reversible subtractor designs based on a new reversible TR gate (TR refers to Thapliyal Ranganathan). In [1] as the quantum gates implementation of the TR gate was not known, only the upper bound on the quantum cost of the reversible subtractors units were established. In this work, we present a new design of the reversible half subtractor based on the quantum gates implementation of the reversible TR gate. The reversible TR gate is designed from 2×2 quantum gates such as CNOT and Controlled-V and Controlled-V + gates. The design of the proposed reversible half subtractor is shown to be better than the design presented in [2], [1] in terms of the quantum cost and delay while maintaining the minimum number of garbage outputs. Further, we present a new design of the reversible full subtractor based on the proposed quantum gates implementation of the TR gate. The proposed reversible full subtractor is optimized in terms of quantum cost, delay and garbage outputs by utilizing the identity property of V and V + reversible gates. The proposed reversible full subtractor is shown to be better than the existing design reported in [3], [1]. The reversible subtractors proposed in this work will be useful in a number of digital signal processing applications.
AB - In [1] we have presented the reversible subtractor designs based on a new reversible TR gate (TR refers to Thapliyal Ranganathan). In [1] as the quantum gates implementation of the TR gate was not known, only the upper bound on the quantum cost of the reversible subtractors units were established. In this work, we present a new design of the reversible half subtractor based on the quantum gates implementation of the reversible TR gate. The reversible TR gate is designed from 2×2 quantum gates such as CNOT and Controlled-V and Controlled-V + gates. The design of the proposed reversible half subtractor is shown to be better than the design presented in [2], [1] in terms of the quantum cost and delay while maintaining the minimum number of garbage outputs. Further, we present a new design of the reversible full subtractor based on the proposed quantum gates implementation of the TR gate. The proposed reversible full subtractor is optimized in terms of quantum cost, delay and garbage outputs by utilizing the identity property of V and V + reversible gates. The proposed reversible full subtractor is shown to be better than the existing design reported in [3], [1]. The reversible subtractors proposed in this work will be useful in a number of digital signal processing applications.
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U2 - 10.1109/NANO.2011.6144350
DO - 10.1109/NANO.2011.6144350
M3 - Conference contribution
AN - SCOPUS:84858990432
SN - 9781457715143
T3 - Proceedings of the IEEE Conference on Nanotechnology
SP - 1430
EP - 1435
BT - 2011 11th IEEE International Conference on Nanotechnology, NANO 2011
T2 - 2011 11th IEEE International Conference on Nanotechnology, NANO 2011
Y2 - 15 August 2011 through 19 August 2011
ER -