A New Reconfigurable Network Node Processor Architecture for Distributed Implementation of Ephemeral State Processing

Ephemeral State Processing (ESP) has been proposed as a lightweight, router-based, scalable building block supporting the construction of new and diverse end-to-end network management and other services. Each node of an ESP enhanced network would require a processor for implementation of the ESP service. An overview and background of ESP is first provided. ESP may be implemented within ESP enhanced network nodes three ways: one way is by a high performance special purpose programmable processor architecture best-fit for ESP implemented to reconfigurable Programmable Logic Device (PLD) technology. This implementation approach is addressed in this manuscript. The manuscript focus is the development, design, implementation, validation and evaluation of a most recently developed special purpose programmable Ephemeral State Processor (ESPR) microarchitecture for the implementation of ESP. Advantages of implementing ESPRs to in-field upgradeable reconfigurable platforms are addressed. A hardware prototype of the newly proposed ESPR microarchitecture is validated via Hardware Description Language (HDL) virtual prototype simulation. The newly proposed ESPR microarchitecture is finally compared to a earlier developed reconfigurable ESPR architecture.