A novel parallel multiply and accumulate (V-MAC) architecture based on ancient Indian Vedic Mathematics

Himanshu Thapliyal, Hamid R. Arabnia

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In this paper new parallel multiply and accumulate ("MAC") is proposed based on algorithm of ancient Indian Vedic Mathematics for high speed applications. In the proposed architecture all bits of operands (multiplier and multiplicand) and accumulator are presented in parallel. The multiplier concurrently adds the partial products bits generated with the accumulator bits. The design implementation is described in both at gate level and high level RTL code (behavioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopsys FPGA Express using: Xilinx, Family: Spartan Svq300, Speed Grade: -4. The present paper relates to improvement in speed/area over MAC architectures implemented in digital signal processors. In FPGA implementation it has been found that the proposed parallel Vedic multiply and accumulate (V-MAC) is faster than multiply and accumulate based on array and Booth multiplier.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Embedded Systems and Applications ESA'04 - Proceedings of the INternational Conference on VLSI, VLSI'04
EditorsH.R. Arabnia, M. Guo, L.T. Yang
Pages440-443
Number of pages4
StatePublished - 2004
EventProceedings of the International Conference on Embedded Systems and Applications ESA'04 - Proceedings of the International Conference on VLSI, VLSI'04 - Las Vegas, NV, United States
Duration: Jun 21 2004Jun 24 2004

Publication series

NameProceedings of the International Conference on Embedded Systems and Applications ESA'04 - Proceedings of the International Conference on VLSI, VLSI'04

Conference

ConferenceProceedings of the International Conference on Embedded Systems and Applications ESA'04 - Proceedings of the International Conference on VLSI, VLSI'04
Country/TerritoryUnited States
CityLas Vegas, NV
Period6/21/046/24/04

Keywords

  • Multiplier
  • Multiply and Accumulate (MAC)
  • Vedic Mathematics

ASJC Scopus subject areas

  • Engineering (all)

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