Abstract
Bit-serial SIMD-parallel execution was once commonly used in supercomputers, but fell out of favor as it became practical to implement word-level operations directly in MIMD hardware. Word-level primitive operations simplify programming and significantly speed-up sequential code. However, aggressive gate-level compiler optimization can dramatically reduce power consumed in massively-parallel bit-serial execution without a performance penalty. The model described here, Parallel Bit Pattern Computing, not only leverages gate-level just-in-time optimization of bit-serial code, but also uses a quantum-inspired type of symbolic execution based on regular expressions to obtain a potentially exponential reduction in computational complexity while using entirely conventional computer hardware.
Original language | English |
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Title of host publication | Languages and Compilers for Parallel Computing - 33rd International Workshop, LCPC 2020 |
Editors | Barbara Chapman, José Moreira |
Pages | 151-159 |
Number of pages | 9 |
DOIs | |
State | Published - 2022 |
Event | 33rd International Workshop on Languages and Compilers for Parallel Computing, LCPC 2020 - Virtual, Online Duration: Oct 14 2020 → Oct 16 2020 |
Publication series
Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
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Volume | 13149 LNCS |
ISSN (Print) | 0302-9743 |
ISSN (Electronic) | 1611-3349 |
Conference
Conference | 33rd International Workshop on Languages and Compilers for Parallel Computing, LCPC 2020 |
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City | Virtual, Online |
Period | 10/14/20 → 10/16/20 |
Bibliographical note
Publisher Copyright:© 2022, Springer Nature Switzerland AG.
Keywords
- Bit-serial SIMD
- C++
- Just in time compilation
- Logic optimization
- Quantum computing
- Qubit
- Regular expressions
ASJC Scopus subject areas
- Theoretical Computer Science
- General Computer Science