An Area and Power Efficient Architecture for Linear Prediction-Error Filters Based on Split Schur Algorithm

Sayed Ahmad Salehi

doi:10.1109/ACSSC.2018.8645071

An Area and Power Efficient Architecture for Linear Prediction-Error Filters Based on Split Schur Algorithm

Sayed Ahmad Salehi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This low-area, low-power digital circuit for computation of linear prediction-error filters for real-valued signals is proposed. Folding technique is used to reduce the number of required arithmetic hardware units to only one multiplier, one divider, and two adders. Modified split Schur algorithm with a less computational complexity than the classical Schur algorithm (and other classical algorithms) is used for implementation. The less algorithmic level computational complexity leads to a hardware with less power consumption. The proposed hardware is synthesized for FPGA implementation and compared with prior architectures of linear-prediction filters in order to demonstrate its efficiency regarding hardware and computational complexity, energy, and execution time.

Original language	English
Title of host publication	Conference Record of the 52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018
Editors	Michael B. Matthews
Pages	231-236
Number of pages	6
ISBN (Electronic)	9781538692189
DOIs	https://doi.org/10.1109/ACSSC.2018.8645071
State	Published - Jul 2 2018
Event	52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018 - Pacific Grove, United States Duration: Oct 28 2018 → Oct 31 2018

Publication series

Name	Conference Record - Asilomar Conference on Signals, Systems and Computers
Volume	2018-October
ISSN (Print)	1058-6393

Conference

Conference	52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018
Country/Territory	United States
City	Pacific Grove
Period	10/28/18 → 10/31/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

Folding transformation
Low-area
Low-power
Schur
split Schur

ASJC Scopus subject areas

Signal Processing
Computer Networks and Communications

Access to Document

10.1109/ACSSC.2018.8645071

Cite this

Salehi, S. A. (2018). An Area and Power Efficient Architecture for Linear Prediction-Error Filters Based on Split Schur Algorithm. In M. B. Matthews (Ed.), Conference Record of the 52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018 (pp. 231-236). Article 8645071 (Conference Record - Asilomar Conference on Signals, Systems and Computers; Vol. 2018-October). https://doi.org/10.1109/ACSSC.2018.8645071

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abstract = "This low-area, low-power digital circuit for computation of linear prediction-error filters for real-valued signals is proposed. Folding technique is used to reduce the number of required arithmetic hardware units to only one multiplier, one divider, and two adders. Modified split Schur algorithm with a less computational complexity than the classical Schur algorithm (and other classical algorithms) is used for implementation. The less algorithmic level computational complexity leads to a hardware with less power consumption. The proposed hardware is synthesized for FPGA implementation and compared with prior architectures of linear-prediction filters in order to demonstrate its efficiency regarding hardware and computational complexity, energy, and execution time.",

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Salehi, SA 2018, An Area and Power Efficient Architecture for Linear Prediction-Error Filters Based on Split Schur Algorithm. in MB Matthews (ed.), Conference Record of the 52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018., 8645071, Conference Record - Asilomar Conference on Signals, Systems and Computers, vol. 2018-October, pp. 231-236, 52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018, Pacific Grove, United States, 10/28/18. https://doi.org/10.1109/ACSSC.2018.8645071

An Area and Power Efficient Architecture for Linear Prediction-Error Filters Based on Split Schur Algorithm. / Salehi, Sayed Ahmad.
Conference Record of the 52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018. ed. / Michael B. Matthews. 2018. p. 231-236 8645071 (Conference Record - Asilomar Conference on Signals, Systems and Computers; Vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Salehi SA. An Area and Power Efficient Architecture for Linear Prediction-Error Filters Based on Split Schur Algorithm. In Matthews MB, editor, Conference Record of the 52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018. 2018. p. 231-236. 8645071. (Conference Record - Asilomar Conference on Signals, Systems and Computers). doi: 10.1109/ACSSC.2018.8645071

An Area and Power Efficient Architecture for Linear Prediction-Error Filters Based on Split Schur Algorithm

Abstract

Publication series

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Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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