An Area and Power Efficient Architecture for Linear Prediction-Error Filters Based on Split Schur Algorithm

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This low-area, low-power digital circuit for computation of linear prediction-error filters for real-valued signals is proposed. Folding technique is used to reduce the number of required arithmetic hardware units to only one multiplier, one divider, and two adders. Modified split Schur algorithm with a less computational complexity than the classical Schur algorithm (and other classical algorithms) is used for implementation. The less algorithmic level computational complexity leads to a hardware with less power consumption. The proposed hardware is synthesized for FPGA implementation and compared with prior architectures of linear-prediction filters in order to demonstrate its efficiency regarding hardware and computational complexity, energy, and execution time.

Original languageEnglish
Title of host publicationConference Record of the 52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018
EditorsMichael B. Matthews
Pages231-236
Number of pages6
ISBN (Electronic)9781538692189
DOIs
StatePublished - Feb 19 2019
Event52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018 - Pacific Grove, United States
Duration: Oct 28 2018Oct 31 2018

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
Volume2018-October
ISSN (Print)1058-6393

Conference

Conference52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018
Country/TerritoryUnited States
CityPacific Grove
Period10/28/1810/31/18

Keywords

  • Folding transformation
  • Low-area
  • Low-power
  • Schur
  • split Schur

ASJC Scopus subject areas

  • Signal Processing
  • Computer Networks and Communications

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