An Area and Power Efficient Architecture for Linear Prediction-Error Filters Based on Split Schur Algorithm

This low-area, low-power digital circuit for computation of linear prediction-error filters for real-valued signals is proposed. Folding technique is used to reduce the number of required arithmetic hardware units to only one multiplier, one divider, and two adders. Modified split Schur algorithm with a less computational complexity than the classical Schur algorithm (and other classical algorithms) is used for implementation. The less algorithmic level computational complexity leads to a hardware with less power consumption. The proposed hardware is synthesized for FPGA implementation and compared with prior architectures of linear-prediction filters in order to demonstrate its efficiency regarding hardware and computational complexity, energy, and execution time.