Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing

Sai Vineel Reddy Chittamuru; Ishan G. Thakkar; Sudeep Pasricha

doi:10.1109/SLIP.2017.7974906

Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing

Sai Vineel Reddy Chittamuru
, Ishan G. Thakkar
, Sudeep Pasricha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

19 Scopus citations

Abstract

Silicon photonic interconnects are being considered for integration in future networks-on-chip (NoCs) as they can enable higher bandwidth and lower latency data transfers at the speed of light. Such photonic interconnects consist of photonic waveguides with dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation and detection. To enable MRs to modulate and detect DWDM photonic signals, carrier injection in MRs through their voltage biasing is essential. But long-term operation of MRs with constant or time-varying temperature and voltage biasing causes aging. Such voltage bias temperature induced (VBTI) aging in MRs leads to resonance wavelength drifts and Q-factor degradation, which increases signal loss and energy delay product in photonic NoCs (PNoCs) that utilize photonic interconnects. This paper explores VBTI aging in MRs and demonstrates its impacts on PNoC architectures for the first time. Our system-level experimental results on two PNoC architectures indicate that VBTI aging increases signal loss in these architectures by up to 7.6dB and increases EDP by up to 26.8% over a span of 5 years.

Original language	English
Title of host publication	2017 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2017
ISBN (Electronic)	9781538615362
DOIs	https://doi.org/10.1109/SLIP.2017.7974906
State	Published - Jul 11 2017
Event	2017 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2017 - Austin, United States Duration: Jun 17 2017 → …

Publication series

Name	International Workshop on System Level Interconnect Prediction, SLIP

Conference

Conference	2017 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2017
Country/Territory	United States
City	Austin
Period	6/17/17 → …

Bibliographical note

Publisher Copyright:
© 2017 ACM.

Funding

This research is supported by grants from SRC, NSF (CCF-1252500, CCF-1302693), and AFOSR (FA9550-13-1-0110).

Funders	Funder number
National Science Foundation (NSF)	CCF-1252500, CCF-1302693
Semiconductor Research Corporation
Air Force Office of Scientific Research, United States Air Force	FA9550-13-1-0110

Keywords

Microring aging
Photonic network on chip
Process variations
Thermal variations

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Computer Science Applications
Applied Mathematics

Access to Document

10.1109/SLIP.2017.7974906

Cite this

Chittamuru, S. V. R., Thakkar, I. G., & Pasricha, S. (2017). Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing. In 2017 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2017 Article 7974906 (International Workshop on System Level Interconnect Prediction, SLIP). https://doi.org/10.1109/SLIP.2017.7974906

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title = "Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing",

abstract = "Silicon photonic interconnects are being considered for integration in future networks-on-chip (NoCs) as they can enable higher bandwidth and lower latency data transfers at the speed of light. Such photonic interconnects consist of photonic waveguides with dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation and detection. To enable MRs to modulate and detect DWDM photonic signals, carrier injection in MRs through their voltage biasing is essential. But long-term operation of MRs with constant or time-varying temperature and voltage biasing causes aging. Such voltage bias temperature induced (VBTI) aging in MRs leads to resonance wavelength drifts and Q-factor degradation, which increases signal loss and energy delay product in photonic NoCs (PNoCs) that utilize photonic interconnects. This paper explores VBTI aging in MRs and demonstrates its impacts on PNoC architectures for the first time. Our system-level experimental results on two PNoC architectures indicate that VBTI aging increases signal loss in these architectures by up to 7.6dB and increases EDP by up to 26.8\% over a span of 5 years.",

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Chittamuru, SVR, Thakkar, IG & Pasricha, S 2017, Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing. in 2017 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2017., 7974906, International Workshop on System Level Interconnect Prediction, SLIP, 2017 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2017, Austin, United States, 6/17/17. https://doi.org/10.1109/SLIP.2017.7974906

Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing. / Chittamuru, Sai Vineel Reddy; Thakkar, Ishan G.; Pasricha, Sudeep.
2017 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2017. 2017. 7974906 (International Workshop on System Level Interconnect Prediction, SLIP).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing

Abstract

Publication series

Conference

Bibliographical note

Funding

Keywords

ASJC Scopus subject areas

Access to Document

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