Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors

Lee Jinju, Kangguo Cheng, Zhi Chen, Karl Hess, Joseph W. Lyding, Kim Young-Kwang, Lee Seung, Kim Young-Wug, Suh Kwang-Pyuk

Research output: Contribution to journalArticlepeer-review

35 Scopus citations

Abstract

We present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO2/Si interface. We have achieved a significant lifetime improvement (90 ×) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.

Original languageEnglish
Pages (from-to)221-223
Number of pages3
JournalIEEE Electron Device Letters
Volume21
Issue number5
DOIs
StatePublished - May 2000

Bibliographical note

Funding Information:
The authors would like to thank Dr. J. Jonas for his helpful discussions and support for building the high pressure furnace. They would also like thank J. E. Baker for her discussions and help on SIMS analysis. The use of the SIMS facility, which was supported by the U.S. Department of Energy, is gratefully acknowledged.

Funding Information:
Manuscript received October 20, 1999; revised February 3, 2000. This work was supported by the Office of Naval Research under Grants N00014-92-J-1519 and N00014-98-I-0604 and by the Beckman Institute for Advanced Science and Technology at the University of Illinois. The review of this letter was arranged by Editor T.-J. King.

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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