Approximate adder circuits using clocked CMOS adiabatic logic (CCAL) for IoT applications

Approximate arithmetic circuitry refers to a class of arithmetic circuits that achieve power and area efficiency through the intentional introduction of inaccuracies into the output behavior of the circuits. Further, low-power adiabatic computing techniques have been proposed as a method for reducing power dissipation. To demonstrate the potential benefit of hybridizing adiabatic and approximate computing, we selected a group of approximate adders and redesigned them using Clocked CMOS Adiabatic Logic (CCAL). We simulated our novel class of adiabatic approximate adders using a 45nm process and Cadence Spectre. The results of our simulations show that the hybridization of approximate and adiabatic techniques reduces power dissipation by 40-56% at 50 MHz compared to approximate CMOS implementations. We conclude that the hybridization of adiabatic and approximate computing would be an excellent design choice for applications with rigid power and area constraints that also boast a tolerance for noise.