Area-Efficient LFSR-Based Stochastic Number Generators with Minimum Correlation

Efficient design of stochastic number generators (SNGs) is critical to the area-efficiency and accuracy of stochastic computing (SC) circuits. Linear feedback shift register (LFSR)-based SNGs are commonly used in SC. To reduce the size of SNGs, we propose a new design approach that shares a combination of the permutations and negations of one LFSR&#x2019;s output for several SNGs. With no hardware overhead, the approach provides SNGs with minimum average SC correlation (SCC) that result in SC circuits with higher accuracy. Compared to the prior state-of-the-art work, our approach produces stochastic bitstreams with 50% less average SCC when a 10-bit LFSR is shared between two SNGs. For an <italic>n</italic>-bit LFSR, the proposed design space consists of <italic>n</italic>! &#x00D7; 2^{<italic>n</italic>} designs and when <italic>n</italic> &#x003E; 7 it is intractable to find the design with minimum SCC by searching the whole space. To address this problem, we propose an optimized search algorithm. For <italic>m</italic> &#x003C; <italic>n</italic>, the extended version of our algorithm can find a set of <italic>m</italic> different designs with minimum SCC values. We apply our approach to SC circuits for digital filters and image processing applications to demonstrate its better computational accuracy and area-efficiency compared to prior work.