ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing

Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

With the rapidly growing use of Convolutional Neural Networks (CNNs) in real-world applications related to machine learning and Artificial Intelligence (Al), several hardware accelerator designs for CNN inference and training have been proposed recently. In this paper, we present ATRIA, a novel bit-pArallel sTochastic aRithmetic based In-DRAM Accelerator for energy-efficient and high-speed inference of CNNs. ATRIA employs light-weight modifications in DRAM cell arrays to implement bit-parallel stochastic arithmetic based acceleration of multiply-accumulate (MAC) operations inside DRAM. ATRIA significantly improves the latency, throughput, and efficiency of processing CNN inferences by performing 16 MAC operations in only five consecutive memory operation cycles. We mapped the inference tasks of four benchmark CNNs on ATRIA to compare its performance with five state-of-the-art in-DRAM CNN accelerators from prior work. The results of our analysis show that ATRIA exhibits only 3.5% drop in CNN inference accuracy and still achieves improvements of up to 3.2× in frames-per-second (FPS) and up to 10× in efficiency (FPS/W/mm2), compared to the best-performing in-DRAM accelerator from prior work.

Original languageEnglish
Title of host publicationProceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
Pages200-205
Number of pages6
ISBN (Electronic)9781665439466
DOIs
StatePublished - Jul 2021
Event20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021 - Tampa, United States
Duration: Jul 7 2021Jul 9 2021

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2021-July
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Conference

Conference20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
Country/TerritoryUnited States
CityTampa
Period7/7/217/9/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

Keywords

  • Convolutional Neural Networks
  • In-Memory Processing
  • Stochastic Arithmetic

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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