Circuit for reversible quantum multiplier based on binary tree optimizing ancilla and garbage bits

Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

52 Scopus citations

Abstract

Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipation less computing and low power computing etc. In reversible logic there exists a one to one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Quantum circuits of many qubits are extremely difficult to realize thus reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature researchers have proposed several designs of reversible quantum multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and the half adders for the addition of partial products increases the overhead in terms of number of ancilla inputs and number of garbage outputs. This paper presents a binary tree based design methodology for a NxN reversible quantum multiplier. The proposed binary tree based design methodology for NxN reversible quantum multiplier performs the addition of partial products in parallel using the reversible ripple quantum adders with no garbage output and ancilla bit, thereby minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows the improvement of 17.86% to 60.34% in terms of ancilla inputs, and 21.43% to 52.17% in terms of garbage outputs compared to all the existing reversible quantum multiplier designs.

Original languageEnglish
Title of host publicationProceedings - 27th International Conference on VLSI Design, VLSID 2014; Held Concurrently with 13th International Conference on Embedded Systems Design
Pages545-550
Number of pages6
DOIs
StatePublished - 2014
Event27th International Conference on VLSI Design, VLSID 2014 - Held Concurrently with 13th International Conference on Embedded Systems Design - Mumbai, India
Duration: Jan 5 2014Jan 9 2014

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Conference

Conference27th International Conference on VLSI Design, VLSID 2014 - Held Concurrently with 13th International Conference on Embedded Systems Design
Country/TerritoryIndia
CityMumbai
Period1/5/141/9/14

Keywords

  • Quantum ALU
  • Quantum Computing
  • Quantum Multiplier

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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