TY - GEN
T1 - Circuit for reversible quantum multiplier based on binary tree optimizing ancilla and garbage bits
AU - Kotiyal, Saurabh
AU - Thapliyal, Himanshu
AU - Ranganathan, Nagarajan
PY - 2014
Y1 - 2014
N2 - Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipation less computing and low power computing etc. In reversible logic there exists a one to one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Quantum circuits of many qubits are extremely difficult to realize thus reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature researchers have proposed several designs of reversible quantum multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and the half adders for the addition of partial products increases the overhead in terms of number of ancilla inputs and number of garbage outputs. This paper presents a binary tree based design methodology for a NxN reversible quantum multiplier. The proposed binary tree based design methodology for NxN reversible quantum multiplier performs the addition of partial products in parallel using the reversible ripple quantum adders with no garbage output and ancilla bit, thereby minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows the improvement of 17.86% to 60.34% in terms of ancilla inputs, and 21.43% to 52.17% in terms of garbage outputs compared to all the existing reversible quantum multiplier designs.
AB - Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipation less computing and low power computing etc. In reversible logic there exists a one to one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Quantum circuits of many qubits are extremely difficult to realize thus reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature researchers have proposed several designs of reversible quantum multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and the half adders for the addition of partial products increases the overhead in terms of number of ancilla inputs and number of garbage outputs. This paper presents a binary tree based design methodology for a NxN reversible quantum multiplier. The proposed binary tree based design methodology for NxN reversible quantum multiplier performs the addition of partial products in parallel using the reversible ripple quantum adders with no garbage output and ancilla bit, thereby minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows the improvement of 17.86% to 60.34% in terms of ancilla inputs, and 21.43% to 52.17% in terms of garbage outputs compared to all the existing reversible quantum multiplier designs.
KW - Quantum ALU
KW - Quantum Computing
KW - Quantum Multiplier
UR - http://www.scopus.com/inward/record.url?scp=84894568797&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84894568797&partnerID=8YFLogxK
U2 - 10.1109/VLSID.2014.101
DO - 10.1109/VLSID.2014.101
M3 - Conference contribution
AN - SCOPUS:84894568797
SN - 9781479925124
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 545
EP - 550
BT - Proceedings - 27th International Conference on VLSI Design, VLSID 2014; Held Concurrently with 13th International Conference on Embedded Systems Design
T2 - 27th International Conference on VLSI Design, VLSID 2014 - Held Concurrently with 13th International Conference on Embedded Systems Design
Y2 - 5 January 2014 through 9 January 2014
ER -