Compiling for SIMD within a register

Randall J. Fisher; Henry G. Dietz

doi:10.1007/3-540-48319-5_19

Compiling for SIMD within a register

Randall J. Fisher, Henry G. Dietz

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

23 Scopus citations

Abstract

Although SIMD (Single Instruction stream Multiple Data stream) parallel computers have existed for decades, it is only in the past few years that a new version of SIMD has evolved: SIMD Within A Register (SWAR). Unlike other styles of SIMD hardware, SWAR models are tuned to be integrated within conventional microprocessors, using their existing memory reference and instruction handling mechanisms, with the primary goal of improving the speed of specific multimedia operations. Because the SWAR implementations for various microprocessors vary widely and each is missing instructions for some SWAR operations that are needed to support a more general, portable, high-level SIMD execution model, this paper focuses on how these missing operations can be implemented using either the existing SWAR hardware or even conventional 32-bit integer instructions. In addition, SWAR offers a few new challenges for compiler optimization, and these are briefly introduced.

Original language	English
Title of host publication	Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings
Editors	Siddhartha Chatterjee, Jan F. Prins, Larry Carter, Jeanne Ferrante, Zhiyuan Li, David Sehr, Pen-Chung Yew
Pages	290-305
Number of pages	16
DOIs	https://doi.org/10.1007/3-540-48319-5_19
State	Published - 1999
Event	11th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1998 - Chapel Hill, United States Duration: Aug 7 1998 → Aug 9 1998

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	1656
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	11th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1998
Country/Territory	United States
City	Chapel Hill
Period	8/7/98 → 8/9/98

Bibliographical note

Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 1999.

ASJC Scopus subject areas

Theoretical Computer Science
General Computer Science

Access to Document

10.1007/3-540-48319-5_19

Cite this

Fisher, R. J., & Dietz, H. G. (1999). Compiling for SIMD within a register. In S. Chatterjee, J. F. Prins, L. Carter, J. Ferrante, Z. Li, D. Sehr, & P.-C. Yew (Eds.), Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings (pp. 290-305). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1656). https://doi.org/10.1007/3-540-48319-5_19

Fisher, Randall J. ; Dietz, Henry G. / Compiling for SIMD within a register. Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings. editor / Siddhartha Chatterjee ; Jan F. Prins ; Larry Carter ; Jeanne Ferrante ; Zhiyuan Li ; David Sehr ; Pen-Chung Yew. 1999. pp. 290-305 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{e562f42c4f504918b015abb1ef72d86d,

title = "Compiling for SIMD within a register",

abstract = "Although SIMD (Single Instruction stream Multiple Data stream) parallel computers have existed for decades, it is only in the past few years that a new version of SIMD has evolved: SIMD Within A Register (SWAR). Unlike other styles of SIMD hardware, SWAR models are tuned to be integrated within conventional microprocessors, using their existing memory reference and instruction handling mechanisms, with the primary goal of improving the speed of specific multimedia operations. Because the SWAR implementations for various microprocessors vary widely and each is missing instructions for some SWAR operations that are needed to support a more general, portable, high-level SIMD execution model, this paper focuses on how these missing operations can be implemented using either the existing SWAR hardware or even conventional 32-bit integer instructions. In addition, SWAR offers a few new challenges for compiler optimization, and these are briefly introduced.",

author = "Fisher, {Randall J.} and Dietz, {Henry G.}",

note = "Publisher Copyright: {\textcopyright} Springer-Verlag Berlin Heidelberg 1999.; 11th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1998 ; Conference date: 07-08-1998 Through 09-08-1998",

year = "1999",

doi = "10.1007/3-540-48319-5_19",

language = "English",

isbn = "3540664262",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

pages = "290--305",

editor = "Siddhartha Chatterjee and Prins, {Jan F.} and Larry Carter and Jeanne Ferrante and Zhiyuan Li and David Sehr and Pen-Chung Yew",

booktitle = "Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings",

}

Fisher, RJ & Dietz, HG 1999, Compiling for SIMD within a register. in S Chatterjee, JF Prins, L Carter, J Ferrante, Z Li, D Sehr & P-C Yew (eds), Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 1656, pp. 290-305, 11th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1998, Chapel Hill, United States, 8/7/98. https://doi.org/10.1007/3-540-48319-5_19

Compiling for SIMD within a register. / Fisher, Randall J.; Dietz, Henry G.
Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings. ed. / Siddhartha Chatterjee; Jan F. Prins; Larry Carter; Jeanne Ferrante; Zhiyuan Li; David Sehr; Pen-Chung Yew. 1999. p. 290-305 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1656).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Compiling for SIMD within a register

AU - Fisher, Randall J.

AU - Dietz, Henry G.

N1 - Publisher Copyright: © Springer-Verlag Berlin Heidelberg 1999.

PY - 1999

Y1 - 1999

N2 - Although SIMD (Single Instruction stream Multiple Data stream) parallel computers have existed for decades, it is only in the past few years that a new version of SIMD has evolved: SIMD Within A Register (SWAR). Unlike other styles of SIMD hardware, SWAR models are tuned to be integrated within conventional microprocessors, using their existing memory reference and instruction handling mechanisms, with the primary goal of improving the speed of specific multimedia operations. Because the SWAR implementations for various microprocessors vary widely and each is missing instructions for some SWAR operations that are needed to support a more general, portable, high-level SIMD execution model, this paper focuses on how these missing operations can be implemented using either the existing SWAR hardware or even conventional 32-bit integer instructions. In addition, SWAR offers a few new challenges for compiler optimization, and these are briefly introduced.

AB - Although SIMD (Single Instruction stream Multiple Data stream) parallel computers have existed for decades, it is only in the past few years that a new version of SIMD has evolved: SIMD Within A Register (SWAR). Unlike other styles of SIMD hardware, SWAR models are tuned to be integrated within conventional microprocessors, using their existing memory reference and instruction handling mechanisms, with the primary goal of improving the speed of specific multimedia operations. Because the SWAR implementations for various microprocessors vary widely and each is missing instructions for some SWAR operations that are needed to support a more general, portable, high-level SIMD execution model, this paper focuses on how these missing operations can be implemented using either the existing SWAR hardware or even conventional 32-bit integer instructions. In addition, SWAR offers a few new challenges for compiler optimization, and these are briefly introduced.

UR - http://www.scopus.com/inward/record.url?scp=84947912725&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84947912725&partnerID=8YFLogxK

U2 - 10.1007/3-540-48319-5_19

DO - 10.1007/3-540-48319-5_19

M3 - Conference contribution

AN - SCOPUS:84947912725

SN - 3540664262

SN - 9783540664260

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 290

EP - 305

BT - Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings

A2 - Chatterjee, Siddhartha

A2 - Prins, Jan F.

A2 - Carter, Larry

A2 - Ferrante, Jeanne

A2 - Li, Zhiyuan

A2 - Sehr, David

A2 - Yew, Pen-Chung

T2 - 11th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1998

Y2 - 7 August 1998 through 9 August 1998

ER -

Fisher RJ, Dietz HG. Compiling for SIMD within a register. In Chatterjee S, Prins JF, Carter L, Ferrante J, Li Z, Sehr D, Yew PC, editors, Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings. 1999. p. 290-305. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/3-540-48319-5_19

Compiling for SIMD within a register

Abstract

Publication series

Conference

Bibliographical note

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this