TY - GEN
T1 - Compiling for SIMD within a register
AU - Fisher, Randall J.
AU - Dietz, Henry G.
PY - 1999
Y1 - 1999
N2 - Although SIMD (Single Instruction stream Multiple Data stream) parallel computers have existed for decades, it is only in the past few years that a new version of SIMD has evolved: SIMD Within A Register (SWAR). Unlike other styles of SIMD hardware, SWAR models are tuned to be integrated within conventional microprocessors, using their existing memory reference and instruction handling mechanisms, with the primary goal of improving the speed of specific multimedia operations. Because the SWAR implementations for various microprocessors vary widely and each is missing instructions for some SWAR operations that are needed to support a more general, portable, high-level SIMD execution model, this paper focuses on how these missing operations can be implemented using either the existing SWAR hardware or even conventional 32-bit integer instructions. In addition, SWAR offers a few new challenges for compiler optimization, and these are briefly introduced.
AB - Although SIMD (Single Instruction stream Multiple Data stream) parallel computers have existed for decades, it is only in the past few years that a new version of SIMD has evolved: SIMD Within A Register (SWAR). Unlike other styles of SIMD hardware, SWAR models are tuned to be integrated within conventional microprocessors, using their existing memory reference and instruction handling mechanisms, with the primary goal of improving the speed of specific multimedia operations. Because the SWAR implementations for various microprocessors vary widely and each is missing instructions for some SWAR operations that are needed to support a more general, portable, high-level SIMD execution model, this paper focuses on how these missing operations can be implemented using either the existing SWAR hardware or even conventional 32-bit integer instructions. In addition, SWAR offers a few new challenges for compiler optimization, and these are briefly introduced.
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U2 - 10.1007/3-540-48319-5_19
DO - 10.1007/3-540-48319-5_19
M3 - Conference contribution
AN - SCOPUS:84947912725
SN - 3540664262
SN - 9783540664260
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 290
EP - 305
BT - Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings
A2 - Chatterjee, Siddhartha
A2 - Prins, Jan F.
A2 - Carter, Larry
A2 - Ferrante, Jeanne
A2 - Li, Zhiyuan
A2 - Sehr, David
A2 - Yew, Pen-Chung
Y2 - 7 August 1998 through 9 August 1998
ER -