Conservative QCA gate (CQCA) for designing concurrently testable molecular QCA circuits

Himanshu Thapliyal, Nagarajan Ranganathan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

45 Scopus citations

Abstract

Nanocircuits based on molecular QCA are prone to high error rates. In this paper, we present a novel conservative logic gate termed 'CQCA' (conservative QCA) to design concurrently testable circuits for molecular QCA. In conservative logic gates, there would be an equal number of 1s in the output as there would be on the input. Thus, conservative logic gates are parity preserving, that is, the parity of the input vectors is equal to the output vectors. CQCA is proposed in this work as molecular QCA is based on majority voting. We analyzed the fault patterns in existing popular conservative Fredkin gate and proposed CQCA gate due to single missing/additional cell defect in molecular QCA. We found that if there is a fault in molecular QCA implementation of Fredkin and CQCA gates, there is a parity mismatch between the input and the output; otherwise the input parity is same as output parity. Thus, any permanent and transient fault in molecular QCA can be concurrently detected if implemented with conservative Fredkin and CQCA gates. We applied novel method of using majority and minority voting to detect the fault in conservative gates. We propose to use CQCA gate compared to existing popular Fredkin gate as CQCA excels Fredkin gate in parameters of complexity(number of majority voter), speed and area. The results are well supported by synthesizing standard benchmark combinational functions. The QCA design of 2 pair 2 rail checker is also presented for the first time ever in literature. The design of QCA layouts and the verification of the designs are performed using the QCADesigner and HDLQ tools.

Original languageEnglish
Title of host publicationProceedings
Subtitle of host publication22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
Pages511-516
Number of pages6
DOIs
StatePublished - 2009
Event22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems - New Delhi, India
Duration: Jan 5 2009Jan 9 2009

Publication series

NameProceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems

Conference

Conference22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
Country/TerritoryIndia
CityNew Delhi
Period1/5/091/9/09

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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