Cross-Layer thermal reliability management in silicon photonic networks-on-Chip

Sudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan G. Thakkar

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations


Silicon photonics technology is being considered for future networks-on-chip (NoCs) as it can enable high bandwidth density and lower latency with traversal of data at the speed of light. But the operation of photonic NoCs (PNoCs) is very sensitive to on-chip temperature variations. These variations can create significant reliability issues for PNoCs. This paper presents a run-time cross-layer framework to overcome temperature variation-induced reliability issues in PNoCs. The framework consists of a device-level reactive mechanism and a system-level proactive technique to avoid on-chip thermal threshold violations and mitigate thermal reliability issues. Our analysis indicates that this framework can reliably satisfy on-chip thermal thresholds and maintain high network bandwidth while reducing power dissipation over state-of-the-art solutions.

Original languageEnglish
Title of host publicationGLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI
Number of pages6
ISBN (Electronic)9781450357241
StatePublished - May 30 2018
Event28th Great Lakes Symposium on VLSI, GLSVLSI 2018 - Chicago, United States
Duration: May 23 2018May 25 2018

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


Conference28th Great Lakes Symposium on VLSI, GLSVLSI 2018
Country/TerritoryUnited States

Bibliographical note

Publisher Copyright:
© 2018 Association of Computing Machinery.


  • Cross-layer design
  • Photonic network on chip
  • Thermal management

ASJC Scopus subject areas

  • General Engineering


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