Cross-Layer thermal reliability management in silicon photonic networks-on-Chip

Sudeep Pasricha; Sai Vineel Reddy Chittamuru; Ishan G. Thakkar

doi:10.1145/3194554.3194608

Cross-Layer thermal reliability management in silicon photonic networks-on-Chip

Sudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan G. Thakkar

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Silicon photonics technology is being considered for future networks-on-chip (NoCs) as it can enable high bandwidth density and lower latency with traversal of data at the speed of light. But the operation of photonic NoCs (PNoCs) is very sensitive to on-chip temperature variations. These variations can create significant reliability issues for PNoCs. This paper presents a run-time cross-layer framework to overcome temperature variation-induced reliability issues in PNoCs. The framework consists of a device-level reactive mechanism and a system-level proactive technique to avoid on-chip thermal threshold violations and mitigate thermal reliability issues. Our analysis indicates that this framework can reliably satisfy on-chip thermal thresholds and maintain high network bandwidth while reducing power dissipation over state-of-the-art solutions.

Original language	English
Title of host publication	GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI
Pages	317-322
Number of pages	6
ISBN (Electronic)	9781450357241
DOIs	https://doi.org/10.1145/3194554.3194608
State	Published - May 30 2018
Event	28th Great Lakes Symposium on VLSI, GLSVLSI 2018 - Chicago, United States Duration: May 23 2018 → May 25 2018

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference	28th Great Lakes Symposium on VLSI, GLSVLSI 2018
Country/Territory	United States
City	Chicago
Period	5/23/18 → 5/25/18

Bibliographical note

Publisher Copyright:
© 2018 Association of Computing Machinery.

Keywords

Cross-layer design
Photonic network on chip
Thermal management

ASJC Scopus subject areas

General Engineering

Access to Document

10.1145/3194554.3194608

Cite this

@inproceedings{c1e71ecc336344288d6786338056ad3a,

title = "Cross-Layer thermal reliability management in silicon photonic networks-on-Chip",

abstract = "Silicon photonics technology is being considered for future networks-on-chip (NoCs) as it can enable high bandwidth density and lower latency with traversal of data at the speed of light. But the operation of photonic NoCs (PNoCs) is very sensitive to on-chip temperature variations. These variations can create significant reliability issues for PNoCs. This paper presents a run-time cross-layer framework to overcome temperature variation-induced reliability issues in PNoCs. The framework consists of a device-level reactive mechanism and a system-level proactive technique to avoid on-chip thermal threshold violations and mitigate thermal reliability issues. Our analysis indicates that this framework can reliably satisfy on-chip thermal thresholds and maintain high network bandwidth while reducing power dissipation over state-of-the-art solutions.",

keywords = "Cross-layer design, Photonic network on chip, Thermal management",

author = "Sudeep Pasricha and {Reddy Chittamuru}, {Sai Vineel} and Thakkar, {Ishan G.}",

note = "Publisher Copyright: {\textcopyright} 2018 Association of Computing Machinery.; 28th Great Lakes Symposium on VLSI, GLSVLSI 2018 ; Conference date: 23-05-2018 Through 25-05-2018",

year = "2018",

month = may,

day = "30",

doi = "10.1145/3194554.3194608",

language = "English",

series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

pages = "317--322",

booktitle = "GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI",

}

Pasricha, S, Reddy Chittamuru, SV & Thakkar, IG 2018, Cross-Layer thermal reliability management in silicon photonic networks-on-Chip. in GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pp. 317-322, 28th Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, United States, 5/23/18. https://doi.org/10.1145/3194554.3194608

Cross-Layer thermal reliability management in silicon photonic networks-on-Chip. / Pasricha, Sudeep; Reddy Chittamuru, Sai Vineel; Thakkar, Ishan G.
GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI. 2018. p. 317-322 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Cross-Layer thermal reliability management in silicon photonic networks-on-Chip

AU - Pasricha, Sudeep

AU - Reddy Chittamuru, Sai Vineel

AU - Thakkar, Ishan G.

PY - 2018/5/30

Y1 - 2018/5/30

N2 - Silicon photonics technology is being considered for future networks-on-chip (NoCs) as it can enable high bandwidth density and lower latency with traversal of data at the speed of light. But the operation of photonic NoCs (PNoCs) is very sensitive to on-chip temperature variations. These variations can create significant reliability issues for PNoCs. This paper presents a run-time cross-layer framework to overcome temperature variation-induced reliability issues in PNoCs. The framework consists of a device-level reactive mechanism and a system-level proactive technique to avoid on-chip thermal threshold violations and mitigate thermal reliability issues. Our analysis indicates that this framework can reliably satisfy on-chip thermal thresholds and maintain high network bandwidth while reducing power dissipation over state-of-the-art solutions.

AB - Silicon photonics technology is being considered for future networks-on-chip (NoCs) as it can enable high bandwidth density and lower latency with traversal of data at the speed of light. But the operation of photonic NoCs (PNoCs) is very sensitive to on-chip temperature variations. These variations can create significant reliability issues for PNoCs. This paper presents a run-time cross-layer framework to overcome temperature variation-induced reliability issues in PNoCs. The framework consists of a device-level reactive mechanism and a system-level proactive technique to avoid on-chip thermal threshold violations and mitigate thermal reliability issues. Our analysis indicates that this framework can reliably satisfy on-chip thermal thresholds and maintain high network bandwidth while reducing power dissipation over state-of-the-art solutions.

KW - Cross-layer design

KW - Photonic network on chip

KW - Thermal management

UR - http://www.scopus.com/inward/record.url?scp=85049460579&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85049460579&partnerID=8YFLogxK

U2 - 10.1145/3194554.3194608

DO - 10.1145/3194554.3194608

M3 - Conference contribution

AN - SCOPUS:85049460579

T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

SP - 317

EP - 322

BT - GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI

T2 - 28th Great Lakes Symposium on VLSI, GLSVLSI 2018

Y2 - 23 May 2018 through 25 May 2018

ER -

Cross-Layer thermal reliability management in silicon photonic networks-on-Chip

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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