The gradually widening speed disparity between CPU and memory has become an overwhelming bottleneck for the development of chip multiprocessor systems. In addition, increasing penalties caused by frequent on-chip memory accesses have raised critical challenges in delivering high memory access performance with tight power and latency budgets. To overcome the daunting memory wall and energy wall issues, this paper focuses on proposing a new heterogeneous scratchpad memory architecture, which is configured from SRAM, MRAM, and Z-RAM. Based on this architecture, we propose a genetic algorithm to perform data allocation to different memory units, therefore, reducing memory access cost in terms of power consumption and latency. Extensive and experiments are performed to show the merits of the heterogeneous scratchpad architecture over the traditional pure memory system and the effectiveness of the proposed algorithms.
|Number of pages||12|
|Journal||IEEE Transactions on Emerging Topics in Computing|
|State||Published - 2015|
Bibliographical noteFunding Information:
The work of M. Qiu was supported by the Division of Computer and Network Systems (CNS) through the National Science Foundation (NSF) under Grant CNS-1457506, Grant CNS-1359557, and Grant CNS-1249223. The work of Z. Zong was supported by NSF CNS-1305359. The work of J. Niu was supported by the National Natural Science Foundation of China under Grant 61170296 and Grant 61190125. The work of G. Quan was supported by NSF under Grant CNS-1423137 and Grant CNS-1018108.
© 2015 IEEE.
- Hybrid memory
- chip multiprocessor
- data allocation
- genetic algorithm
ASJC Scopus subject areas
- Computer Science (miscellaneous)
- Information Systems
- Human-Computer Interaction
- Computer Science Applications