TY - GEN
T1 - Design and analysis of A VLSI based high performance low power parallel square architecture
AU - Thapliyal, Himanshu
AU - Srinivas, M. B.
AU - Arabnia, Hamid R.
PY - 2005
Y1 - 2005
N2 - The present paper proposes a novel square algorithm and architecture based on the Duplex property of Urdhva Triyakbhyam (the multiplication algorithm given in the ancient Indian Vedic Mathematics). It is an object of the present paper to provide a square computation circuit which can reduce circuit size by eliminating unnecessary logic in comparison to computing the square with a dedicated multiplier. The proposed architecture is efficient in terms of silicon area/speed/power compared to using multipliers for performing square operation.
AB - The present paper proposes a novel square algorithm and architecture based on the Duplex property of Urdhva Triyakbhyam (the multiplication algorithm given in the ancient Indian Vedic Mathematics). It is an object of the present paper to provide a square computation circuit which can reduce circuit size by eliminating unnecessary logic in comparison to computing the square with a dedicated multiplier. The proposed architecture is efficient in terms of silicon area/speed/power compared to using multipliers for performing square operation.
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M3 - Conference contribution
AN - SCOPUS:60749092500
SN - 9781932415636
T3 - Proceedings of the 2005 International Conference on Algorithmic Mathematics and Computer Science, AMCS'05
SP - 72
EP - 76
BT - Proceedings of the 2005 International Conference on Algorithmic Mathematics and Computer Science, AMCS'05
T2 - 2005 International Conference on Algorithmic Mathematics and Computer Science, AMCS'05
Y2 - 20 June 2005 through 23 June 2005
ER -