Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware

Adiabatic logic is one of the circuit design techniques for designing energy-efficient hardware. In recent years, it has also been proved that this technique is suitable for designing secure hardware. In the existing literature, a Secured Quasi-Adiabatic Logic Family (SQAL) has recently been proposed in designing Differential Power Analysis (DPA)-resistant and energy-efficient hardware. SQAL shows improvement over all other existing DPA-resistant adiabatic logic in terms of energy dissipation and area-overhead. However, the drawback is, SQAL suffers from non-adiabatic energy loss during the evaluation of the outputs. To minimize the non-adiabatic loss, we propose a novel Symmetric Pass Gate Adiabatic Logic (SPGAL). SPICE simulations show that the bit-parallel cellular multiplier over GF(2⁴) that we implemented using SPGAL saves up to 81% of energy as compared to SQAL at 12.5 MHz. Calculated values of Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) show that the proposed logic gates based on SPGAL consume uniform energy for every cycle of operation irrespective of their input transition. The uniform energy rate and low power operation shows that the proposed SPGAL is energy-efficient in nature and would be resistant to DPA attack at the circuit level.