Abstract
Implementation of a five-input majority gate, full adder, and full subtractor using multiple layers in nanomagnetic logic is proposed. Correct functionality of the designs was verified through the use of a special purpose Verilog library.
Original language | English |
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Pages (from-to) | 1618-1620 |
Number of pages | 3 |
Journal | Electronics Letters |
Volume | 52 |
Issue number | 19 |
DOIs | |
State | Published - Sep 15 2016 |
Bibliographical note
Publisher Copyright:© The Institution of Engineering and Technology 2016.
ASJC Scopus subject areas
- Electrical and Electronic Engineering