Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing

C. Labrado, H. Thapliyal

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

Implementation of a five-input majority gate, full adder, and full subtractor using multiple layers in nanomagnetic logic is proposed. Correct functionality of the designs was verified through the use of a special purpose Verilog library.

Original languageEnglish
Pages (from-to)1618-1620
Number of pages3
JournalElectronics Letters
Volume52
Issue number19
DOIs
StatePublished - Sep 15 2016

Bibliographical note

Publisher Copyright:
© The Institution of Engineering and Technology 2016.

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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