Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing

C. Labrado; H. Thapliyal

doi:10.1049/el.2016.2294

Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing

C. Labrado, H. Thapliyal

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

Implementation of a five-input majority gate, full adder, and full subtractor using multiple layers in nanomagnetic logic is proposed. Correct functionality of the designs was verified through the use of a special purpose Verilog library.

Original language	English
Pages (from-to)	1618-1620
Number of pages	3
Journal	Electronics Letters
Volume	52
Issue number	19
DOIs	https://doi.org/10.1049/el.2016.2294
State	Published - Sep 15 2016

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© The Institution of Engineering and Technology 2016.

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el.2016.2294

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abstract = "Implementation of a five-input majority gate, full adder, and full subtractor using multiple layers in nanomagnetic logic is proposed. Correct functionality of the designs was verified through the use of a special purpose Verilog library.",

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Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing

Abstract

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