TY - GEN
T1 - Design of a reversible floating-point adder architecture
AU - Nachtigal, Michael
AU - Thapliyal, Himanshu
AU - Ranganathan, Nagarajan
PY - 2011
Y1 - 2011
N2 - The study of reversible circuits holds great promise for emerging technologies. Reversible circuits offer the possibility for great reductions in power consumption, and quantum computers will require logically reversible digital circuits. Many different reversible implementations of logical and arithmetic units have been proposed in the literature, but very few reversible floating-point designs exist. Floating-point operations are needed very frequently in nearly all computing disciplines, and studies have shown floating-point addition to be the most oft used floating-point operation. In this paper we present for the first time a reversible floating-point adder that closely follows the IEEE754 specification for binary floating-point arithmetic. Our design requires reversible designs of a controlled swap unit, a subtracter, an alignment unit, signed integer representation conversion units, an integer adder, a normalization unit, and a rounding unit. We analyze these major components in terms of quantum cost, garbage outputs, and constant inputs.
AB - The study of reversible circuits holds great promise for emerging technologies. Reversible circuits offer the possibility for great reductions in power consumption, and quantum computers will require logically reversible digital circuits. Many different reversible implementations of logical and arithmetic units have been proposed in the literature, but very few reversible floating-point designs exist. Floating-point operations are needed very frequently in nearly all computing disciplines, and studies have shown floating-point addition to be the most oft used floating-point operation. In this paper we present for the first time a reversible floating-point adder that closely follows the IEEE754 specification for binary floating-point arithmetic. Our design requires reversible designs of a controlled swap unit, a subtracter, an alignment unit, signed integer representation conversion units, an integer adder, a normalization unit, and a rounding unit. We analyze these major components in terms of quantum cost, garbage outputs, and constant inputs.
KW - Reversible logic
KW - addition
KW - arithmetic
KW - floating-point
KW - quantum computing
UR - http://www.scopus.com/inward/record.url?scp=84858955696&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84858955696&partnerID=8YFLogxK
U2 - 10.1109/NANO.2011.6144358
DO - 10.1109/NANO.2011.6144358
M3 - Conference contribution
AN - SCOPUS:84858955696
SN - 9781457715143
T3 - Proceedings of the IEEE Conference on Nanotechnology
SP - 451
EP - 456
BT - 2011 11th IEEE International Conference on Nanotechnology, NANO 2011
T2 - 2011 11th IEEE International Conference on Nanotechnology, NANO 2011
Y2 - 15 August 2011 through 19 August 2011
ER -