Design of efficient reversible binary subtractors based on a new reversible gate

Himanshu Thapliyal; Nagarajan Ranganathan

doi:10.1109/ISVLSI.2009.49

Design of efficient reversible binary subtractors based on a new reversible gate

Himanshu Thapliyal, Nagarajan Ranganathan

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

134 Scopus citations

Abstract

Reversible logic has extensive applications in quantum computing, low power VLSI design, quantum dot cellular automata and optical computing. While several researchers have investigated the design of reversible logic elements, there is not much work reported on reversible binary subtractors. In this paper, we propose the design of a new reversible gate called TR gate. Further, we investigate the design of reversible binary subtractors based on the proposed TR gate. The proposed TR gate is better for designing reversible binary subtractor compared to such gates discussed in literature in terms of quantum cost, garbage outputs and complexity of gates.

Original language	English
Title of host publication	Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009
Pages	229-234
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2009.49
State	Published - 2009
Event	2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009 - Tampa, FL, United States Duration: May 14 2009 → May 15 2009

Publication series

Name	Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009

Conference

Conference	2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009
Country/Territory	United States
City	Tampa, FL
Period	5/14/09 → 5/15/09

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ISVLSI.2009.49

Cite this

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title = "Design of efficient reversible binary subtractors based on a new reversible gate",

abstract = "Reversible logic has extensive applications in quantum computing, low power VLSI design, quantum dot cellular automata and optical computing. While several researchers have investigated the design of reversible logic elements, there is not much work reported on reversible binary subtractors. In this paper, we propose the design of a new reversible gate called TR gate. Further, we investigate the design of reversible binary subtractors based on the proposed TR gate. The proposed TR gate is better for designing reversible binary subtractor compared to such gates discussed in literature in terms of quantum cost, garbage outputs and complexity of gates.",

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note = "2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009 ; Conference date: 14-05-2009 Through 15-05-2009",

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Thapliyal, H & Ranganathan, N 2009, Design of efficient reversible binary subtractors based on a new reversible gate. in Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009., 5076412, Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp. 229-234, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, Tampa, FL, United States, 5/14/09. https://doi.org/10.1109/ISVLSI.2009.49

Design of efficient reversible binary subtractors based on a new reversible gate. / Thapliyal, Himanshu; Ranganathan, Nagarajan.
Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009. 2009. p. 229-234 5076412 (Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Design of efficient reversible binary subtractors based on a new reversible gate

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