Design of Quantum Circuits for Galois Field Squaring and Exponentiation

Edgard Muñoz-Coreas; Himanshu Thapliyal

doi:10.1109/ISVLSI.2017.21

Design of Quantum Circuits for Galois Field Squaring and Exponentiation

Edgard Muñoz-Coreas, Himanshu Thapliyal

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

This work presents an algorithm to generate depth, quantum gate and qubit optimized circuits for GF(2m) squaring in the polynomial basis. Further, to the best of our knowledge the proposed quantum squaring circuit algorithm is the only work that considers depth as a metric to be optimized. We compared circuits generated by our proposed algorithm against the state of the art and determine that they require 50% fewer qubits and offer gates savings that range from 37% to 68%. Further, existing quantum exponentiation are based on either modular or integer arithmetic. However, Galois arithmetic is a useful tool to design resource efficient quantum exponentiation circuit applicable in quantum cryptanalysis. Therefore, we present the quantum circuit implementation of Galois field exponentiation based on the proposed quantum Galois field squaring circuit. We calculated a qubit savings ranging between 44% to 50% and quantum gate savings ranging between 37% to 68% compared to identical quantum exponentiation circuit based on existing squaring circuits.

Original language	English
Title of host publication	Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Editors	Ricardo Reis, Mircea Stan, Michael Huebner, Nikolaos Voros
Pages	68-73
Number of pages	6
ISBN (Electronic)	9781509067626
DOIs	https://doi.org/10.1109/ISVLSI.2017.21
State	Published - Jul 20 2017
Event	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 - Bochum, North Rhine-Westfalia, Germany Duration: Jul 3 2017 → Jul 5 2017

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2017-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Conference

Conference	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Country/Territory	Germany
City	Bochum, North Rhine-Westfalia
Period	7/3/17 → 7/5/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

Galois field arithmetic
quantum computing

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2017.21

Cite this

Muñoz-Coreas, E., & Thapliyal, H. (2017). Design of Quantum Circuits for Galois Field Squaring and Exponentiation. In R. Reis, M. Stan, M. Huebner, & N. Voros (Eds.), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 (pp. 68-73). Article 7987497 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July). https://doi.org/10.1109/ISVLSI.2017.21

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title = "Design of Quantum Circuits for Galois Field Squaring and Exponentiation",

abstract = "This work presents an algorithm to generate depth, quantum gate and qubit optimized circuits for GF(2m) squaring in the polynomial basis. Further, to the best of our knowledge the proposed quantum squaring circuit algorithm is the only work that considers depth as a metric to be optimized. We compared circuits generated by our proposed algorithm against the state of the art and determine that they require 50% fewer qubits and offer gates savings that range from 37% to 68%. Further, existing quantum exponentiation are based on either modular or integer arithmetic. However, Galois arithmetic is a useful tool to design resource efficient quantum exponentiation circuit applicable in quantum cryptanalysis. Therefore, we present the quantum circuit implementation of Galois field exponentiation based on the proposed quantum Galois field squaring circuit. We calculated a qubit savings ranging between 44% to 50% and quantum gate savings ranging between 37% to 68% compared to identical quantum exponentiation circuit based on existing squaring circuits.",

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doi = "10.1109/ISVLSI.2017.21",

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Muñoz-Coreas, E & Thapliyal, H 2017, Design of Quantum Circuits for Galois Field Squaring and Exponentiation. in R Reis, M Stan, M Huebner & N Voros (eds), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017., 7987497, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2017-July, pp. 68-73, 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, North Rhine-Westfalia, Germany, 7/3/17. https://doi.org/10.1109/ISVLSI.2017.21

Design of Quantum Circuits for Galois Field Squaring and Exponentiation. / Muñoz-Coreas, Edgard; Thapliyal, Himanshu.
Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. ed. / Ricardo Reis; Mircea Stan; Michael Huebner; Nikolaos Voros. 2017. p. 68-73 7987497 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Design of Quantum Circuits for Galois Field Squaring and Exponentiation

Abstract

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Bibliographical note

Keywords

ASJC Scopus subject areas

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