Abstract
In this work, we have proposed an implementation of a testable reversible adder using conservative reversible logic for Spintronics based nanomagnetic logic (NML). The testable adder has the advantage that all unidirectional stuck at faults can be detected concurrently while the circuit is performing the normal operation. Further, the unidirectional faults can also be tested offline using only two test vectors, all 0's and all 1's. Two methodologies for the design of testable reversible ripple carry adder are investigated. The first method makes use of two different logic blocks that can be cascaded to form reversible ripple carry adders. The second method is a classical approach in which full adders are cascaded in ripple carry fashion. The promising finding of this work is that even though method 1 is an attractive choice to design testable reversible adders in quantum computing, for NML computing method 2 is attractive because of its improvement in propagation delay and NML cost.
Original language | English |
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Title of host publication | Proceedings - 2015 IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2015 |
Pages | 107-111 |
Number of pages | 5 |
ISBN (Electronic) | 9781467396912 |
DOIs | |
State | Published - Mar 15 2016 |
Event | 1st IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2015 - Indore, India Duration: Dec 21 2015 → Dec 23 2015 |
Publication series
Name | Proceedings - 2015 IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2015 |
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Conference
Conference | 1st IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2015 |
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Country/Territory | India |
City | Indore |
Period | 12/21/15 → 12/23/15 |
Bibliographical note
Publisher Copyright:© 2015 IEEE.
Keywords
- Fredkin gate
- Nanomagnetic Logic Computing
- Spintronics
- reversible logic
ASJC Scopus subject areas
- Computer Science Applications
- Hardware and Architecture
- Information Systems