TY - GEN
T1 - Design, synthesis and test of reversible circuits for emerging nanotechnologies
AU - Thapliyal, Himanshu
AU - Ranganathan, Nagarajan
PY - 2012
Y1 - 2012
N2 - Reversible circuits can generate unique output vector from each input vector, and vice-versa, that is, there is a one-to-one mapping between the input and the output vectors. The contributions of the dissertation include a novel reversible gate particularly suitable for reversible arithmetic, several designs for reversible arithmetic such as binary and BCD adders, sub tractors and comparators, a set of reversible sequential circuits such as latches, flip-flops, and shift registers. Unlike previous works, the above designs are optimized for multiple parameters such as ancilla and garbage bits, quantum cost and delay. Another important contribution is the application of conservative reversible logic towards online and offline testing of single as well as multiple faults in reversible as well as traditional logic VLSI circuits.
AB - Reversible circuits can generate unique output vector from each input vector, and vice-versa, that is, there is a one-to-one mapping between the input and the output vectors. The contributions of the dissertation include a novel reversible gate particularly suitable for reversible arithmetic, several designs for reversible arithmetic such as binary and BCD adders, sub tractors and comparators, a set of reversible sequential circuits such as latches, flip-flops, and shift registers. Unlike previous works, the above designs are optimized for multiple parameters such as ancilla and garbage bits, quantum cost and delay. Another important contribution is the application of conservative reversible logic towards online and offline testing of single as well as multiple faults in reversible as well as traditional logic VLSI circuits.
KW - Conservative Logic
KW - Quantum Computing
KW - Quantum Dot Cellular Automata
KW - Reversible Logic
KW - TR Gate
UR - http://www.scopus.com/inward/record.url?scp=84867827618&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84867827618&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2012.83
DO - 10.1109/ISVLSI.2012.83
M3 - Conference contribution
AN - SCOPUS:84867827618
SN - 9780769547671
T3 - Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
SP - 5
EP - 6
BT - Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
T2 - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Y2 - 19 August 2012 through 21 August 2012
ER -