Dynamic barrier architecture for multi-mode fine-grain parallelism using conventional processors

W. E. Cohen, H. G. Dietz, J. B. Sponaugle

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations

Abstract

Parallel computers constructed using conventional processors offer the potential to achieve large improvements in execution speed at reasonable cost, however, these machines tend to efficiently implement only coarse-grain MIMD parallelism. To achieve the best possible speedup through parallel execution, a computer must be capable of effectively using all the different types of parallelism that exist in each program. A combination of SIMD, VLIW, and MIMD parallelism, at a variety of granularity levels, exists in most applications; thus, hardware that can support multiple types of parallelism can achieve better performance with a wider range of codes. In this paper, we introduce a new hardware barrier architecture that provides the full DBM functionality we discussed in [11], but can be implemented with much simpler hardware. This mechanism can be used to efficiently support multi-mode moderate-width parallelism with instruction-level granularity (i.e., synchronization cost is approximately one LOAD instruction).

Original languageEnglish
Title of host publicationProceedings of the 1994 International Conference on Parallel Processing, ICPP 1994
PagesI93-I96
DOIs
StatePublished - 1994
Event23rd International Conference on Parallel Processing, ICPP 1994 - Raleigh, NC, United States
Duration: Aug 15 1994Aug 19 1994

Publication series

NameProceedings of the International Conference on Parallel Processing
Volume1
ISSN (Print)0190-3918

Conference

Conference23rd International Conference on Parallel Processing, ICPP 1994
Country/TerritoryUnited States
CityRaleigh, NC
Period8/15/948/19/94

ASJC Scopus subject areas

  • Software
  • Mathematics (all)
  • Hardware and Architecture

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