DyPhase: A dynamic phase change memory architecture with symmetric write latency and restorable endurance

Ishan G. Thakkar, Sudeep Pasricha

Research output: Contribution to journalArticlepeer-review

12 Scopus citations

Abstract

A major challenge for the widespread adoption of phase change memory (PCM) as main memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation (i.e., an operation that writes "1") is 2-5 times longer than the latency of a RESET operation (i.e., an operation that writes "0"). For this reason, the average write latency of a PCM system is limited by the high-latency SET operations. This paper presents a novel PCM architecture called DyPhase, which uses partial-SET operations instead of the conventional SET operations to introduce a symmetry in write latency, thereby increasing write performance and throughput. However, use of partial-SET decreases data retention time. As a remedy to this problem, DyPhase employs novel distributed refresh operations in PCM that leverage the available power budget to periodically rewrite the stored data with minimal performance overhead. Unfortunately, the use of periodic refresh operations increases the write rate of the memory, which in turn accelerates memory degradation and decreases its lifetime. DyPhase overcomes this shortcoming by utilizing a proactive in-situ self-annealing (PISA) technique that periodically heals degraded memory cells, resulting in decelerated degradation and increased memory lifetime. Experiments with PARSEC benchmarks indicate that our DyPhase architecture-based hybrid dynamic random access memory (DRAM)-PCM memory system, when enabled with PISA, yields orders of magnitude higher lifetime, 8.3% less CPI, and 44.3% less EDP on average over other hybrid DRAM-PCM memory systems that utilize PCM architectures from prior works.

Original languageEnglish
Article number8067442
Pages (from-to)1760-1773
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume37
Issue number9
DOIs
StatePublished - Sep 2018

Bibliographical note

Publisher Copyright:
© 1982-2012 IEEE.

Keywords

  • Asymmetric write latency
  • distributed refresh
  • endurance
  • lifetime
  • phase change memory (PCM)

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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