DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency

Ishan G. Thakkar, Sudeep Pasricha

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

A major challenge for the widespread adoption of phase change memory (PCM) as main memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation (i.e., an operation that writes '1') is 2-5 times longer than the latency of a RESET operation (i.e., an operation that writes '0'). For this reason, the average write latency of a PCM system is limited by the high-latency SET operations. This paper presents a novel PCM architecture called DyPhase, which uses partial-SET operations instead of the conventional SET operations to introduce a symmetry in write latency, thereby increasing write performance and throughput. However, use of partial-SET decreases data retention time. As a remedy to this problem, DyPhase employs novel distributed refresh operations in PCM that leverage the available power budget to periodically rewrite the stored data with minimal performance overhead. Experiments with PARSEC benchmarks indicate that our DyPhase architecture achieves 16.2% less average latency and 27.6% less EDP on average over other PCM architectures from prior works.

Original languageEnglish
Title of host publicationProceedings - 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems, VLSID 2017
Pages41-46
Number of pages6
ISBN (Electronic)9781509057405
DOIs
StatePublished - Mar 21 2017
Event30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems, VLSID 2017 - Hyderabad, India
Duration: Jan 7 2017Jan 11 2017

Publication series

NameProceedings - 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems, VLSID 2017

Conference

Conference30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems, VLSID 2017
Country/TerritoryIndia
CityHyderabad
Period1/7/171/11/17

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Keywords

  • Asymmetric write latency
  • Distributed refresh
  • Endurance
  • Lifetime
  • Phase change memory

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

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