Efficient hardware implementation of discrete wavelet transform based on stochastic computing

Sayed Ahmad Salehi, Durjoy Deb Dhruba

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Stochastic Computing (SC) provides cost-efficient and fault-tolerant computing circuits and has been used for implementing different algorithms. This paper studies the hardware-efficient implementation of discrete wavelet transform (DWT) with SC, for the first time. We design SC circuits using both lifting scheme (LS) and filter bank (FB) models of DWT. We present our approach for CDF 5/3 and CDF 9/7, two DWTs used for JPEG 2000, and discuss some circuit-level optimizations to improve the hardware-efficiency and computational accuracy of the proposed circuits. The FPGA implementation results show that, compared to binary computing, SC achieves remarkably better performance in terms of area, power, speed and fault tolerance.

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020
Pages422-427
Number of pages6
ISBN (Electronic)9781728157757
DOIs
StatePublished - Jul 2020
Event19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020 - Limassol, Cyprus
Duration: Jul 6 2020Jul 8 2020

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2020-July
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Conference

Conference19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020
Country/TerritoryCyprus
CityLimassol
Period7/6/207/8/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

  • Discrete wavelet transform (DWT)
  • Fault tolerance
  • Filter bank (FB)
  • Lifting scheme (LS)
  • Stochastic computing (SC)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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