Eliminating Memory Fragmentation within Partitionable SIMD/SPMD Machines

Mark A. Nichols; Howard Jay Siegel; Henry G. Dietz; Russell W. Quong; Wayne G. Nation

doi:10.1109/71.86105

Eliminating Memory Fragmentation within Partitionable SIMD/SPMD Machines

Mark A. Nichols, Howard Jay Siegel, Henry G. Dietz, Russell W. Quong, Wayne G. Nation

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

Efficient data layout is an important aspect of the compilation process. A model for the creation of “perfect” memory maps for large-scale parallel machines capable of user-controlled partitionable SIMD/SPMD operation is developed. The term “perfect” implies that no memory fragmentation occurs and ensures that the memory map size is kept to a minimum. The major constraint on solving this problem is one based on the single program nature of both the SIMD and SPMD modes of parallelism. Specifically, it is assumed all processors within the same submachine use identical addresses to access corresponding data items in each of their local memories. Necessary and sufficient conditions are derived for being able to create “perfect” memory maps and these results are applied to several partitionable interconnection networks.

Original language	English
Pages (from-to)	290-303
Number of pages	14
Journal	IEEE Transactions on Parallel and Distributed Systems
Volume	2
Issue number	3
DOIs	https://doi.org/10.1109/71.86105
State	Published - Jul 1991

Keywords

Compilers
Partitionable machines
interconnection networks
memory fragmentation
parallel processing
parallel processing

ASJC Scopus subject areas

Signal Processing
Hardware and Architecture
Computational Theory and Mathematics

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10.1109/71.86105

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title = "Eliminating Memory Fragmentation within Partitionable SIMD/SPMD Machines",

abstract = "Efficient data layout is an important aspect of the compilation process. A model for the creation of “perfect” memory maps for large-scale parallel machines capable of user-controlled partitionable SIMD/SPMD operation is developed. The term “perfect” implies that no memory fragmentation occurs and ensures that the memory map size is kept to a minimum. The major constraint on solving this problem is one based on the single program nature of both the SIMD and SPMD modes of parallelism. Specifically, it is assumed all processors within the same submachine use identical addresses to access corresponding data items in each of their local memories. Necessary and sufficient conditions are derived for being able to create “perfect” memory maps and these results are applied to several partitionable interconnection networks.",

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AB - Efficient data layout is an important aspect of the compilation process. A model for the creation of “perfect” memory maps for large-scale parallel machines capable of user-controlled partitionable SIMD/SPMD operation is developed. The term “perfect” implies that no memory fragmentation occurs and ensures that the memory map size is kept to a minimum. The major constraint on solving this problem is one based on the single program nature of both the SIMD and SPMD modes of parallelism. Specifically, it is assumed all processors within the same submachine use identical addresses to access corresponding data items in each of their local memories. Necessary and sufficient conditions are derived for being able to create “perfect” memory maps and these results are applied to several partitionable interconnection networks.

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Eliminating Memory Fragmentation within Partitionable SIMD/SPMD Machines

Abstract

Keywords

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