TY - GEN
T1 - Energy-efficient magnetic circuits based on nanoelectronic devices
AU - Sharifi, Fazel
AU - Thapliyal, Himanshu
PY - 2017/9/25
Y1 - 2017/9/25
N2 - As CMOS technology scales down to the nanoscale, high leakage power consumption becomes the main problem and challenge of electronic circuits. To overcome this challenge, nano-emerging technologies and logic-in-memory structure are being studied. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic in memory structures in conjunction with CMOS. In this paper, we present novel designs of hybrid MTJ/CMOS circuits; AND, XOR and 1-bit full adder. The proposed MTJ/CMOS full adder design has 71% lower Power-delay-product (PDP) compared to the previous MTJ/CMOS full adder. To further improve the energy efficiency we investigated the use of nanoelectronic devices (CNFET, FinFET) in the proposed circuits and compared them with the CMOS based designs. The hybrid MTJ/CNFET and MJT/FinFET full adders have about 18 and 11 times lower PDP, respectively, when compared to the MJT/CMOS design. Also, the MTJ/CNFET based full adder has 66% lower PDP than the MTJ/FinFET based design.
AB - As CMOS technology scales down to the nanoscale, high leakage power consumption becomes the main problem and challenge of electronic circuits. To overcome this challenge, nano-emerging technologies and logic-in-memory structure are being studied. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic in memory structures in conjunction with CMOS. In this paper, we present novel designs of hybrid MTJ/CMOS circuits; AND, XOR and 1-bit full adder. The proposed MTJ/CMOS full adder design has 71% lower Power-delay-product (PDP) compared to the previous MTJ/CMOS full adder. To further improve the energy efficiency we investigated the use of nanoelectronic devices (CNFET, FinFET) in the proposed circuits and compared them with the CMOS based designs. The hybrid MTJ/CNFET and MJT/FinFET full adders have about 18 and 11 times lower PDP, respectively, when compared to the MJT/CMOS design. Also, the MTJ/CNFET based full adder has 66% lower PDP than the MTJ/FinFET based design.
KW - CNFET
KW - FinFET
KW - MTJ
KW - Spintronics
UR - http://www.scopus.com/inward/record.url?scp=85032691094&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85032691094&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2017.8050919
DO - 10.1109/ISCAS.2017.8050919
M3 - Conference contribution
AN - SCOPUS:85032691094
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
Y2 - 28 May 2017 through 31 May 2017
ER -
