Energy-efficient magnetic circuits based on nanoelectronic devices

Fazel Sharifi; Himanshu Thapliyal

doi:10.1109/ISCAS.2017.8050919

Energy-efficient magnetic circuits based on nanoelectronic devices

Fazel Sharifi, Himanshu Thapliyal

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

As CMOS technology scales down to the nanoscale, high leakage power consumption becomes the main problem and challenge of electronic circuits. To overcome this challenge, nano-emerging technologies and logic-in-memory structure are being studied. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic in memory structures in conjunction with CMOS. In this paper, we present novel designs of hybrid MTJ/CMOS circuits; AND, XOR and 1-bit full adder. The proposed MTJ/CMOS full adder design has 71% lower Power-delay-product (PDP) compared to the previous MTJ/CMOS full adder. To further improve the energy efficiency we investigated the use of nanoelectronic devices (CNFET, FinFET) in the proposed circuits and compared them with the CMOS based designs. The hybrid MTJ/CNFET and MJT/FinFET full adders have about 18 and 11 times lower PDP, respectively, when compared to the MJT/CMOS design. Also, the MTJ/CNFET based full adder has 66% lower PDP than the MTJ/FinFET based design.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems
Subtitle of host publication	From Dreams to Innovation, ISCAS 2017 - Conference Proceedings
ISBN (Electronic)	9781467368520
DOIs	https://doi.org/10.1109/ISCAS.2017.8050919
State	Published - Sep 25 2017
Event	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States Duration: May 28 2017 → May 31 2017

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Country/Territory	United States
City	Baltimore
Period	5/28/17 → 5/31/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

CNFET
FinFET
MTJ
Spintronics

ASJC Scopus subject areas

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISCAS.2017.8050919

Cite this

@inproceedings{684ae2cffe1346bb86939b0eda204289,

title = "Energy-efficient magnetic circuits based on nanoelectronic devices",

abstract = "As CMOS technology scales down to the nanoscale, high leakage power consumption becomes the main problem and challenge of electronic circuits. To overcome this challenge, nano-emerging technologies and logic-in-memory structure are being studied. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic in memory structures in conjunction with CMOS. In this paper, we present novel designs of hybrid MTJ/CMOS circuits; AND, XOR and 1-bit full adder. The proposed MTJ/CMOS full adder design has 71\% lower Power-delay-product (PDP) compared to the previous MTJ/CMOS full adder. To further improve the energy efficiency we investigated the use of nanoelectronic devices (CNFET, FinFET) in the proposed circuits and compared them with the CMOS based designs. The hybrid MTJ/CNFET and MJT/FinFET full adders have about 18 and 11 times lower PDP, respectively, when compared to the MJT/CMOS design. Also, the MTJ/CNFET based full adder has 66\% lower PDP than the MTJ/FinFET based design.",

keywords = "CNFET, FinFET, MTJ, Spintronics",

author = "Fazel Sharifi and Himanshu Thapliyal",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 ; Conference date: 28-05-2017 Through 31-05-2017",

year = "2017",

month = sep,

day = "25",

doi = "10.1109/ISCAS.2017.8050919",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

booktitle = "IEEE International Symposium on Circuits and Systems",

}

Sharifi, F & Thapliyal, H 2017, Energy-efficient magnetic circuits based on nanoelectronic devices. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050919, Proceedings - IEEE International Symposium on Circuits and Systems, 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 5/28/17. https://doi.org/10.1109/ISCAS.2017.8050919

Energy-efficient magnetic circuits based on nanoelectronic devices. / Sharifi, Fazel; Thapliyal, Himanshu.
IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. 2017. 8050919 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Energy-efficient magnetic circuits based on nanoelectronic devices

AU - Sharifi, Fazel

AU - Thapliyal, Himanshu

PY - 2017/9/25

Y1 - 2017/9/25

N2 - As CMOS technology scales down to the nanoscale, high leakage power consumption becomes the main problem and challenge of electronic circuits. To overcome this challenge, nano-emerging technologies and logic-in-memory structure are being studied. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic in memory structures in conjunction with CMOS. In this paper, we present novel designs of hybrid MTJ/CMOS circuits; AND, XOR and 1-bit full adder. The proposed MTJ/CMOS full adder design has 71% lower Power-delay-product (PDP) compared to the previous MTJ/CMOS full adder. To further improve the energy efficiency we investigated the use of nanoelectronic devices (CNFET, FinFET) in the proposed circuits and compared them with the CMOS based designs. The hybrid MTJ/CNFET and MJT/FinFET full adders have about 18 and 11 times lower PDP, respectively, when compared to the MJT/CMOS design. Also, the MTJ/CNFET based full adder has 66% lower PDP than the MTJ/FinFET based design.

AB - As CMOS technology scales down to the nanoscale, high leakage power consumption becomes the main problem and challenge of electronic circuits. To overcome this challenge, nano-emerging technologies and logic-in-memory structure are being studied. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic in memory structures in conjunction with CMOS. In this paper, we present novel designs of hybrid MTJ/CMOS circuits; AND, XOR and 1-bit full adder. The proposed MTJ/CMOS full adder design has 71% lower Power-delay-product (PDP) compared to the previous MTJ/CMOS full adder. To further improve the energy efficiency we investigated the use of nanoelectronic devices (CNFET, FinFET) in the proposed circuits and compared them with the CMOS based designs. The hybrid MTJ/CNFET and MJT/FinFET full adders have about 18 and 11 times lower PDP, respectively, when compared to the MJT/CMOS design. Also, the MTJ/CNFET based full adder has 66% lower PDP than the MTJ/FinFET based design.

KW - CNFET

KW - FinFET

KW - MTJ

KW - Spintronics

UR - http://www.scopus.com/inward/record.url?scp=85032691094&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85032691094&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2017.8050919

DO - 10.1109/ISCAS.2017.8050919

M3 - Conference contribution

AN - SCOPUS:85032691094

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - IEEE International Symposium on Circuits and Systems

T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017

Y2 - 28 May 2017 through 31 May 2017

ER -

Energy-efficient magnetic circuits based on nanoelectronic devices

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

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