Enhanced architecture for computing polynomials using unipolar stochastic logic

This paper presents the enhanced stochastic circuits of polynomial computation by combining the synchronizer and the correlation-based subtractor into the architecture proposed by Liu et al. The conventional and simplified synchronizers, which are used to increase the positive correlation between the bit-streams, are mathematically investigated. Analysis reveals that the conventional one generally induces the better result than the simplified one at the expense of more states in the finite state machine (FSM). By manipulating independence and the positive correlation, D flip-flops and the random number sources (RNSs) can be eliminated from the original architecture to reduce hardware complexity. Results show that the proposed designs are superior to the previous one in terms of the computational accuracy and hardware cost.