This paper proposes the hardware implementation of RSA encryption algorithm using the recently proposed hierarchical overlay multiplier architecture. In the hierarchical overlay architecture, we have grouped 4 bits of the multiplier and multiplicand at a time and thereafter apply vertical and crosswise algorithm to decompose whole of the multiplication operation into 4×4 parallel multiply modules. The coding of the RSA is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that RSA hardware implemented using proposed architecture is faster than RSA hardware implemented using traditional multiplication algorithms.
|Title of host publication||Proceedings of The 2005 International Conference on Security and Management, SAM'05|
|Number of pages||5|
|State||Published - 2005|
|Event||2005 International Conference on Security and Management, SAM'05 - Las Vegas, NV, United States|
Duration: Jun 20 2005 → Jun 23 2005
|Name||Proceedings of The 2005 International Conference on Security and Management, SAM'05|
|Conference||2005 International Conference on Security and Management, SAM'05|
|City||Las Vegas, NV|
|Period||6/20/05 → 6/23/05|
Bibliographical noteFunding Information:
The authors wish to thank L. Liu at the College of Geoscience of Northeast Petroleum University for her constructive help. The authors are particularly grateful to S. Busetti, L. Zeng, Z. Liao, and the anonymous reviewers for providing excellent advice on the clarity of the text and figures. This study is financially supported by the National Natural Science Foundation of China (grant nos. 41502124 and U1562214) and China Postdoctoral Science Foundation (grant no. 2015M581424).
ASJC Scopus subject areas
- Computer Networks and Communications
- Hardware and Architecture