Abstract
Spatial-phase locked electron-beam lithography provides feedback control of electron-beam position by monitoring the signal from a fiducial grid on the substrate. Formerly, a real-time spatial-phase-locking algorithm has been implemented on general purpose microprocessor to provide control for raster-scan system. However, it would be advantageous to provide real-time spatial-phase locking for both vector- and raster-scan systems with accelerated sampling and computational rate demanded by many modern electron-beam lithography tools. In addition, it is desirable for the phase-locking system to be easily parallelizable for multibeam/multicolumn systems. Implementation of vector- and raster-scan spatial-phase locking algorithms on a field-programmable gate array (FPGA) addresses both of these issues. Initial experimental results demonstrate that the FPGA implementation can provide real-time spatial-phase locking effectively at accelerated speed even when the algorithm is performed in the noise limited regime.
| Original language | English |
|---|---|
| Pages (from-to) | 2316-2321 |
| Number of pages | 6 |
| Journal | Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures |
| Volume | 26 |
| Issue number | 6 |
| DOIs | |
| State | Published - 2008 |
Bibliographical note
Funding Information:This material was based upon work supported by the National Science Foundation under Grant No. 0601351. Facilities and technical assistance for this work were provided by the University of Kentucky Center for Nanoscale Science and Engineering (CeNSE) which is supported by National Science Foundation EPSCoR under Award No. 0447479. The authors would like to acknowledge Brian Wajdyk and Chuck May ( CENSE ) for their valuable technical assistance as well as the donation of FPGA design tools from Xilinx University Program.
ASJC Scopus subject areas
- Condensed Matter Physics
- Electrical and Electronic Engineering