TY - GEN
T1 - Implementation of a fast square in RSA encryption/decryption architecture
AU - Thapliyal, Himanshu
AU - Srinivas, M. B.
AU - Arabnia, Hamid R.
PY - 2005
Y1 - 2005
N2 - This paper proposes the hardware implementation of RSA encryption algorithm using the recently proposed square architecture. It is an object of the present paper to provide a RSA encryption/ decryption circuit which can reduce circuit size by eliminating unnecessary logic in comparison to computing the square with a dedicated multiplier. The coding of the RSA is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that RSA hardware implemented using the proposed architecture is faster than RSA hardware implemented using traditional multiplication algorithm.
AB - This paper proposes the hardware implementation of RSA encryption algorithm using the recently proposed square architecture. It is an object of the present paper to provide a RSA encryption/ decryption circuit which can reduce circuit size by eliminating unnecessary logic in comparison to computing the square with a dedicated multiplier. The coding of the RSA is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that RSA hardware implemented using the proposed architecture is faster than RSA hardware implemented using traditional multiplication algorithm.
UR - http://www.scopus.com/inward/record.url?scp=62349123870&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=62349123870&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:62349123870
SN - 1932415823
SN - 9781932415827
T3 - Proceedings of The 2005 International Conference on Security and Management, SAM'05
SP - 371
EP - 374
BT - Proceedings of The 2005 International Conference on Security and Management, SAM'05
T2 - 2005 International Conference on Security and Management, SAM'05
Y2 - 20 June 2005 through 23 June 2005
ER -