Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration

Chao Hsuan Huang; Ishan G. Thakkar

doi:10.1109/ICCD50377.2020.00076

Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration

Chao Hsuan Huang, Ishan G. Thakkar

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Over the years, the DRAM latency has not scaled proportionally with its density due to the cost-centric mindset of the DRAM industry. Prior work has shown that this shortcoming can be overcome by reducing the critical length of DRAM access path. However, doing so decreases DRAM area-efficiency, exacerbating the latency-area tradeoffs for DRAM design. In this paper, we show that reorganizing DRAM cell-arrays using the emerging monolithic 3D (M3D) integration technology can improve these fundamental latency-area tradeoffs. Based on our evaluation results for PARSEC benchmarks, our designed M3D DRAM cell-array organizations can yield up to 9.56% less latency and up to 21.21 % less energy-delay product (EDP), with up to 14% less DRAM die area, compared to the conventional 2D DDR4 DRAM.

Original language	English
Title of host publication	Proceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020
Pages	417-420
Number of pages	4
ISBN (Electronic)	9781728197104
DOIs	https://doi.org/10.1109/ICCD50377.2020.00076
State	Published - Oct 2020
Event	38th IEEE International Conference on Computer Design, ICCD 2020 - Hartford, United States Duration: Oct 18 2020 → Oct 21 2020

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Volume	2020-October
ISSN (Print)	1063-6404

Conference

Conference	38th IEEE International Conference on Computer Design, ICCD 2020
Country/Territory	United States
City	Hartford
Period	10/18/20 → 10/21/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

Bitlines
DRAM
DRAM Access Latency
Monolithic 3D Integration
Sense Amplifiers

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD50377.2020.00076

Cite this

Huang, C. H., & Thakkar, I. G. (2020). Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. In Proceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020 (pp. 417-420). Article 9283599 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2020-October). https://doi.org/10.1109/ICCD50377.2020.00076

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Huang, CH & Thakkar, IG 2020, Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. in Proceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020., 9283599, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, vol. 2020-October, pp. 417-420, 38th IEEE International Conference on Computer Design, ICCD 2020, Hartford, United States, 10/18/20. https://doi.org/10.1109/ICCD50377.2020.00076

Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. / Huang, Chao Hsuan; Thakkar, Ishan G.
Proceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020. 2020. p. 417-420 9283599 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2020-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Huang CH, Thakkar IG. Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. In Proceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020. 2020. p. 417-420. 9283599. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). doi: 10.1109/ICCD50377.2020.00076

Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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