Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration

Chao Hsuan Huang, Ishan G. Thakkar

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Over the years, the DRAM latency has not scaled proportionally with its density due to the cost-centric mindset of the DRAM industry. Prior work has shown that this shortcoming can be overcome by reducing the critical length of DRAM access path. However, doing so decreases DRAM area-efficiency, exacerbating the latency-area tradeoffs for DRAM design. In this paper, we show that reorganizing DRAM cell-arrays using the emerging monolithic 3D (M3D) integration technology can improve these fundamental latency-area tradeoffs. Based on our evaluation results for PARSEC benchmarks, our designed M3D DRAM cell-array organizations can yield up to 9.56% less latency and up to 21.21 % less energy-delay product (EDP), with up to 14% less DRAM die area, compared to the conventional 2D DDR4 DRAM.

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020
Pages417-420
Number of pages4
ISBN (Electronic)9781728197104
DOIs
StatePublished - Oct 2020
Event38th IEEE International Conference on Computer Design, ICCD 2020 - Hartford, United States
Duration: Oct 18 2020Oct 21 2020

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Volume2020-October
ISSN (Print)1063-6404

Conference

Conference38th IEEE International Conference on Computer Design, ICCD 2020
Country/TerritoryUnited States
CityHartford
Period10/18/2010/21/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

  • Bitlines
  • DRAM
  • DRAM Access Latency
  • Monolithic 3D Integration
  • Sense Amplifiers

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration'. Together they form a unique fingerprint.

Cite this