In-memory Bulk Bitwise Logic Operation for Multi-level Cell Non-volatile Memories

Multi-level cell (MLC) memories are of particular interest due to their high density and low per-bit cost. The significant contrast between high and low resistance states in phase change memory (PCM) technology supports its MLC capability. In this paper, we propose a processing-in-memory (PIM) structure for resistance-based, including PCM, MLC (2-bit/cell) memories. With slight modification of the existing peripheral circuitry of PCM, the proposed structure enables performing in-memory bulk logic operations. The modified peripheral circuitry activates two rows of PCM cells simultaneously, reads their bitlines, and converts them to desired outputs to compute the bitwise operation for pairs of bits stored in the activated cells. Unlike PIM structures based on single-level cell (SLC) that process rows of single bits in each memory access, the proposed MLC-based structure processes rows of 2 bits in each memory access. This leads to a significant saving in computational time and energy. Our evaluation for bitwise vector OR operations shows significant improvement in computational speed and energy compared to state-of-the-art work using SLC. Future development of software support for the proposed structure, will enable us to efficiently perform complex image processing and deep neural network algorithms in memory.