Interface properties of Si3N4Si/n-GaAs metal-msulator-semiconductor structure using a Si interlayer

Dae Gyu Park, Zhi Chen, Andrei E. Botchkarev, S. Noor Mohammad, Hadis Morkoç

Research output: Contribution to journalArticlepeer-review

20 Scopus citations


We report the effects of Si interlayer on the capacitance-voltage (C-V) characteristics of Si3N4/Si/n-GaAs metal-insulator-semiconductor (MIS) capacitor as a function of interfacial Si thickness, Si growth temperature and post-growth annealing. The thickness of interfacial Si was found to be the most pivotal parameter for the best interface properties as determined by the comprehensive C-V and conductance measurements. The minimum interface trap density Dit of 5×1010eV−1cm−2 near midgap is realized with a Si interlayer of 10 A. The hysteresis and frequency dispersion of the GaAs MIS capacitor were lower than 50 mV, and some of them as low as 30 mV under a field swing of about ±1.3 MV cm−1. Ex-situ solid-phase annealing (SPA) at 550°C in N2 using rapid thermal annealing was sufficient to recrystallize the as-deposited Si interlayer at a low temperature (less than 400°C). The minimum Dit thus obtained using ex-situ SPA was less than 1·5 × 1011 eV−1 cm−2 regardless of Si deposition temperature. 1 MHz frequency response at 80 K requires that the traps be within 35meV of the conduction band of GaAs. The effects of SPA and post-growth annealing on the interface stability are also discussed.

Original languageEnglish
Pages (from-to)219-234
Number of pages16
JournalPhilosophical Magazine B: Physics of Condensed Matter; Statistical Mechanics, Electronic, Optical and Magnetic Properties
Issue number3
StatePublished - Sep 1996

ASJC Scopus subject areas

  • General Chemical Engineering
  • General Physics and Astronomy


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