Interface properties of Si₃N₄Si/n-GaAs metal-msulator-semiconductor structure using a Si interlayer

We report the effects of Si interlayer on the capacitance-voltage (C-V) characteristics of Si₃N₄/Si/n-GaAs metal-insulator-semiconductor (MIS) capacitor as a function of interfacial Si thickness, Si growth temperature and post-growth annealing. The thickness of interfacial Si was found to be the most pivotal parameter for the best interface properties as determined by the comprehensive C-V and conductance measurements. The minimum interface trap density D_it of 5×10¹⁰eV⁻¹cm⁻² near midgap is realized with a Si interlayer of 10 A. The hysteresis and frequency dispersion of the GaAs MIS capacitor were lower than 50 mV, and some of them as low as 30 mV under a field swing of about ±1.3 MV cm⁻¹. Ex-situ solid-phase annealing (SPA) at 550°C in N₂ using rapid thermal annealing was sufficient to recrystallize the as-deposited Si interlayer at a low temperature (less than 400°C). The minimum D_it thus obtained using ex-situ SPA was less than 1·5 × 10¹¹ eV⁻¹ cm⁻² regardless of Si deposition temperature. 1 MHz frequency response at 80 K requires that the traps be within 35meV of the conduction band of GaAs. The effects of SPA and post-growth annealing on the interface stability are also discussed.