Investigation of lifting-based hardware architectures for discrete wavelet transform

Sayed Ahmad Salehi, Saeed Sadri

Research output: Contribution to journalArticlepeer-review

9 Scopus citations


This paper investigates efficient hardware architectures for implementation of 1-D and 2-D discrete wavelet transforms (DWTs). The architectures are based on the lifting scheme. We propose a general structure to minimize the number of multipliers and adders for 1-D DWTs. Compared to previous conventional architectures, the architecture presented here is more efficient in terms of the required arithmetic units. Moreover, we describe a new frame scan method for a block-based 2-D DWT structure which provides a flexible trade-off between the required internal memory size and external memory access. In contrast, other 2-D DWT structures require a fixed memory size.

Original languageEnglish
Pages (from-to)1-16
Number of pages16
JournalCircuits, Systems, and Signal Processing
Issue number1
StatePublished - 2009


  • Block-based scan method
  • DWT
  • Field programmable gate array
  • Lifting scheme

ASJC Scopus subject areas

  • Signal Processing
  • Applied Mathematics


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